1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2023-03-28 luobeihai first version 9 */ 10 11 #ifndef __DRV_SDRAM_H__ 12 #define __DRV_SDRAM_H__ 13 14 /* parameters for sdram peripheral */ 15 /* Bank1 or Bank2 */ 16 #define SDRAM_TARGET_BANK 1 17 /* apm32f407 Bank Addr: 0x60000000 */ 18 #define SDRAM_BANK_ADDR ((uint32_t)0x60000000) 19 /* data width: 8, 16, 32 */ 20 #define SDRAM_DATA_WIDTH 16 21 /* column bit numbers */ 22 #define SDRAM_COLUMN_BITS DMC_COL_WIDTH_8 23 /* row bit numbers */ 24 #define SDRAM_ROW_BITS DMC_ROW_WIDTH_11 25 26 #define SDRAM_MEMORY_SIZE DMC_MEMORY_SIZE_2MB 27 28 #define SDRAM_SIZE ((uint32_t)0x200000) 29 30 /* memory mode register */ 31 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) 32 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) 33 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) 34 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) 35 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) 36 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) 37 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) 38 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) 39 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) 40 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 41 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) 42 43 #endif 44