1 //*****************************************************************************
2 //
3 //  am_hal_cachectrl.h
4 //! @file
5 //!
6 //! @brief Functions for accessing and configuring the CACHE controller.
7 //
8 //*****************************************************************************
9 
10 //*****************************************************************************
11 //
12 // Copyright (c) 2017, Ambiq Micro
13 // All rights reserved.
14 //
15 // Redistribution and use in source and binary forms, with or without
16 // modification, are permitted provided that the following conditions are met:
17 //
18 // 1. Redistributions of source code must retain the above copyright notice,
19 // this list of conditions and the following disclaimer.
20 //
21 // 2. Redistributions in binary form must reproduce the above copyright
22 // notice, this list of conditions and the following disclaimer in the
23 // documentation and/or other materials provided with the distribution.
24 //
25 // 3. Neither the name of the copyright holder nor the names of its
26 // contributors may be used to endorse or promote products derived from this
27 // software without specific prior written permission.
28 //
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 // POSSIBILITY OF SUCH DAMAGE.
40 //
41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package.
42 //
43 //*****************************************************************************
44 #ifndef AM_HAL_CACHECTRL_H
45 #define AM_HAL_CACHECTRL_H
46 
47 //*****************************************************************************
48 //
49 // Cache configuration structure
50 //
51 //*****************************************************************************
52 typedef struct
53 {
54     //
55     //! Set to 1 to enable the cache.
56     //
57     uint8_t ui32EnableCache;
58 
59     //
60     //! Set to 1 to enable the LRU cache replacement policy.
61     //! Set to 0 to enable the LRR (least recently used) replacement policy.
62     //! LEE minimizes writes to the TAG SRAM.
63     //
64     uint8_t ui32LRU;
65 
66     //
67     //! Set to 3 to enable non-cachable region 1 and non-cachable region 0.
68     //! Set to 2 to enable non-cachable region 1.
69     //! Set to 1 to enable non-cachable region 0.
70     //! Set to 0 to make all regions cacheable.
71     //
72     uint8_t ui32EnableNCregions;
73 
74     //
75     //! Set to:
76     //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 for direct-mapped,
77     //!     128-bit linesize, 256 entries (2 SRAMs active)
78     //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256 for two-way set associative,
79     //!     128-bit linesize, 256 entries (4 SRAMs active)
80     //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512 for two-way set associative,
81     //!     128-bit linesize, 512 entries (8 SRAMs active)
82     //
83     uint8_t ui32Config;
84 
85     //
86     //! Set to 1 to enable serial cache mode.
87     //
88     uint8_t ui32SerialCacheMode;
89 
90     //
91     //! Set to 3 to enable flash data caching and flash instruction caching.
92     //! Set to 2 to enable flash data caching.
93     //! Set to 1 to enable flash instruction caching.
94     //! Set to 0 to disable flash data caching and flash instruction caching.
95     //
96     uint8_t ui32FlashCachingEnables;
97 
98     //
99     //! Set to 1 to enable clock gating of cache RAMs.
100     //
101     uint8_t ui32EnableCacheClockGating;
102 
103     //
104     //! Set to 1 to enable light sleep of cache RAMs.
105     //
106     uint8_t ui32EnableLightSleep;
107 
108     //
109     //! Set Data RAM delay value (0x0 - 0xF).
110     //
111     uint8_t ui32Dly;
112 
113     //
114     //! Set SM Data RAM delay value (0x0 - 0xF).
115     //
116     uint8_t ui32SMDly;
117 
118     //
119     //! Set to 1 to enable clock gating of the entire data array.
120     //
121     uint8_t ui32EnableDataClockGating;
122 
123     //
124     //! Set to 1 to enable cache monitor statistics.
125     //
126     uint8_t ui32EnableCacheMonitoring;
127 }
128 am_hal_cachectrl_config_t;
129 
130 extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults;
131 
132 //*****************************************************************************
133 //
134 //! @name Cache enables
135 //! @brief Configuration selection for the various cache enables.
136 //!
137 //! These macros may be used in conjunction with the
138 //!  am_hal_cachectrl_cache_enable() function to enable various cache features.
139 //!
140 //! @{
141 //
142 //*****************************************************************************
143 #define AM_HAL_CACHECTRL_CACHECFG_ENABLE                AM_REG_CACHECTRL_CACHECFG_ENABLE_M
144 #define AM_HAL_CACHECTRL_CACHECFG_LRU_ENABLE            AM_REG_CACHECTRL_CACHECFG_LRU_M
145 #define AM_HAL_CACHECTRL_CACHECFG_NC0_ENABLE            AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M
146 #define AM_HAL_CACHECTRL_CACHECFG_NC1_ENABLE            AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M
147 #define AM_HAL_CACHECTRL_CACHECFG_SERIAL_ENABLE         AM_REG_CACHECTRL_CACHECFG_SERIAL_M
148 #define AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE         AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M
149 #define AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE         AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M
150 #define AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE  AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M
151 #define AM_HAL_CACHECTRL_CACHECFG_LS_ENABLE             AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M
152 #define AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE   AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M
153 #define AM_HAL_CACHECTRL_CACHECFG_MONITOR_ENABLE        AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M
154 //! @}
155 
156 //*****************************************************************************
157 //
158 //! @name Cache Config
159 //! @brief Configuration selection for the cache.
160 //!
161 //! These macros may be used in conjunction with the
162 //!  am_hal_cachectrl_cache_config() function to select the cache type.
163 //!
164 //! @{
165 //
166 //*****************************************************************************
167 #define AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 AM_REG_CACHECTRL_CACHECFG_CONFIG_W1_128B_256E
168 #define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256   AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_256E
169 #define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512   AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E
170 //! @}
171 
172 //*****************************************************************************
173 //
174 // Default cache settings
175 //
176 //*****************************************************************************
177 #define AM_HAL_CACHECTRL_DEFAULTS                                             \
178     (AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE |                                \
179      AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE |                                \
180      AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE |                         \
181      AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE |                          \
182      AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512)
183 
184 #ifdef __cplusplus
185 extern "C"
186 {
187 #endif
188 
189 //*****************************************************************************
190 //
191 // External function definitions
192 //
193 //*****************************************************************************
194 extern void am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig);
195 extern void am_hal_cachectrl_disable(void);
196 extern void am_hal_cachectrl_config_default(void);
197 extern void am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig);
198 extern uint32_t am_hal_cachectrl_cache_enables(uint32_t u32EnableMask,
199                                                uint32_t u32DisableMask);
200 extern void am_hal_cachectrl_cache_config(uint32_t ui32CacheConfig);
201 extern void am_hal_cachectrl_invalidate_flash_cache(void);
202 extern void am_hal_cachectrl_reset_statistics(void);
203 extern uint32_t am_hal_cachectrl_sleep_mode_status(void);
204 extern uint32_t am_hal_cachectrl_sleep_mode_enable(uint32_t ui32EnableMask,
205                                                    uint32_t ui32DisableMask);
206 
207 #ifdef __cplusplus
208 }
209 #endif
210 
211 #endif // AM_HAL_CACHECTRL_H
212