1 //*****************************************************************************
2 //
3 //  am_hal_clkgen.h
4 //! @file
5 //!
6 //! @brief Functions for accessing and configuring the CLKGEN.
7 //
8 //*****************************************************************************
9 
10 //*****************************************************************************
11 //
12 // Copyright (c) 2017, Ambiq Micro
13 // All rights reserved.
14 //
15 // Redistribution and use in source and binary forms, with or without
16 // modification, are permitted provided that the following conditions are met:
17 //
18 // 1. Redistributions of source code must retain the above copyright notice,
19 // this list of conditions and the following disclaimer.
20 //
21 // 2. Redistributions in binary form must reproduce the above copyright
22 // notice, this list of conditions and the following disclaimer in the
23 // documentation and/or other materials provided with the distribution.
24 //
25 // 3. Neither the name of the copyright holder nor the names of its
26 // contributors may be used to endorse or promote products derived from this
27 // software without specific prior written permission.
28 //
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 // POSSIBILITY OF SUCH DAMAGE.
40 //
41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package.
42 //
43 //*****************************************************************************
44 #ifndef AM_HAL_CLKGEN_H
45 #define AM_HAL_CLKGEN_H
46 
47 //*****************************************************************************
48 //
49 //! @name System Clock max frequency
50 //! @brief Defines the maximum clock frequency for this device.
51 //!
52 //! These macros provide a definition of the maximum clock frequency.
53 //!
54 //! @{
55 //
56 //*****************************************************************************
57 #define AM_HAL_CLKGEN_FREQ_MAX_HZ       48000000
58 #define AM_HAL_CLKGEN_FREQ_MAX_MHZ      (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000000)
59 //! @}
60 
61 //*****************************************************************************
62 //
63 //! @name System Clock Selection
64 //! @brief Divisor selection for the main system clock.
65 //!
66 //! These macros may be used along with the am_hal_clkgen_sysctl_select()
67 //! function to select the frequency of the main system clock.
68 //!
69 //! @{
70 //
71 //*****************************************************************************
72 #define AM_HAL_CLKGEN_SYSCLK_MAX        AM_REG_CLKGEN_CCTRL_CORESEL_HFRC
73 #define AM_HAL_CLKGEN_SYSCLK_48MHZ      AM_REG_CLKGEN_CCTRL_CORESEL_HFRC
74 //! @}
75 
76 //*****************************************************************************
77 //
78 //! @name Interrupt Status Bits
79 //! @brief Interrupt Status Bits for enable/disble use
80 //!
81 //! These macros may be used to set and clear interrupt bits.
82 //! @{
83 //
84 //*****************************************************************************
85 #define AM_HAL_CLKGEN_INT_ALM           AM_REG_CLKGEN_INTEN_ALM_M
86 #define AM_HAL_CLKGEN_INT_OF            AM_REG_CLKGEN_INTEN_OF_M
87 #define AM_HAL_CLKGEN_INT_ACC           AM_REG_CLKGEN_INTEN_ACC_M
88 #define AM_HAL_CLKGEN_INT_ACF           AM_REG_CLKGEN_INTEN_ACF_M
89 //! @}
90 
91 //*****************************************************************************
92 //
93 //! @name OSC Start and Stop
94 //! @brief OSC Start and Stop defines.
95 //!
96 //! OSC Start and Stop defines to be used with \e am_hal_clkgen_osc_x().
97 //! @{
98 //
99 //*****************************************************************************
100 #define AM_HAL_CLKGEN_OSC_LFRC          AM_REG_CLKGEN_OCTRL_STOPRC_M
101 #define AM_HAL_CLKGEN_OSC_XT            AM_REG_CLKGEN_OCTRL_STOPXT_M
102 //! @}
103 
104 //*****************************************************************************
105 //
106 // OSC Start, Stop, Select defines
107 //
108 //*****************************************************************************
109 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC         AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC
110 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2      AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2
111 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV4      AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4
112 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8      AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8
113 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV16     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16
114 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV32     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32
115 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_RTC_100Hz    AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_100Hz
116 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2M     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M
117 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT           AM_REG_CLKGEN_CLKOUT_CKSEL_XT
118 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_CG_100Hz     AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz
119 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC         AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC
120 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4    AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4
121 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8    AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8
122 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32   AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32
123 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64   AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64
124 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128
125 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256
126 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLK     AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLK
127 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_FLASH_CLK    AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK
128 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2    AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2
129 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32   AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32
130 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512  AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512
131 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K  AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K
132 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV256    AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256
133 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8K     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K
134 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV64K    AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K
135 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16  AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16
136 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128
137 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz    AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz
138 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K  AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K
139 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M  AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M
140 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K
141 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M
142 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M   AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M
143 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE       AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE
144 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8
145 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE   AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE
146 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE         AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE
147 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16   AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16
148 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32
149 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_FCLKNE       AM_REG_CLKGEN_CLKOUT_CKSEL_FCLKNE
150 #define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE       AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE
151 
152 //*****************************************************************************
153 //
154 // UARTEN
155 //
156 //*****************************************************************************
157 #define AM_HAL_CLKGEN_UARTEN_DIS          AM_REG_CLKGEN_UARTEN_UART0EN_DIS
158 #define AM_HAL_CLKGEN_UARTEN_EN           AM_REG_CLKGEN_UARTEN_UART0EN_EN
159 #define AM_HAL_CLKGEN_UARTEN_REDUCE_FREQ  AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ
160 #define AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV
161 
162 #define AM_HAL_CLKGEN_UARTEN_UARTENn_S(module)                                  \
163         ((module) *                                                             \
164         (AM_REG_CLKGEN_UARTEN_UART1EN_S - AM_REG_CLKGEN_UARTEN_UART0EN_S))
165 
166 #define AM_HAL_CLKGEN_UARTEN_UARTENn_M(module)                                  \
167         (AM_REG_CLKGEN_UARTEN_UART0EN_M << AM_HAL_CLKGEN_UARTEN_UARTENn_S(module))
168 
169 //
170 // UARTEN: entype is one of DIS, EN, REDUCE_FREQ, EN_POWER_SAV.
171 //
172 #define AM_HAL_CLKGEN_UARTEN_UARTENn(module, entype)                            \
173         (AM_REG_CLKGEN_UARTEN_UART0EN_##entype <<                               \
174          AM_HAL_CLKGEN_UARTEN_UARTENn_S(module))
175 
176 #ifdef __cplusplus
177 extern "C"
178 {
179 #endif
180 
181 //*****************************************************************************
182 //
183 // External function definitions
184 //
185 //*****************************************************************************
186 extern void am_hal_clkgen_sysclk_select(uint32_t ui32ClockSetting);
187 extern uint32_t am_hal_clkgen_sysclk_get(void);
188 extern void am_hal_clkgen_osc_start(uint32_t ui32OscFlags);
189 extern void am_hal_clkgen_osc_stop(uint32_t ui32OscFlags);
190 extern void am_hal_clkgen_clkout_enable(uint32_t ui32Signal);
191 extern void am_hal_clkgen_clkout_disable(void);
192 extern void am_hal_clkgen_uarten_set(uint32_t ui32Module, uint32_t ui32UartEn);
193 extern void am_hal_clkgen_int_enable(uint32_t ui32Interrupt);
194 extern uint32_t am_hal_clkgen_int_enable_get(void);
195 extern void am_hal_clkgen_int_disable(uint32_t ui32Interrupt);
196 extern void am_hal_clkgen_int_clear(uint32_t ui32Interrupt);
197 extern void am_hal_clkgen_int_set(uint32_t ui32Interrupt);
198 extern uint32_t am_hal_clkgen_int_status_get(bool bEnabledOnly);
199 extern void am_hal_clkgen_hfrc_adjust_enable(uint32_t ui32Warmup, uint32_t ui32Frequency);
200 extern void am_hal_clkgen_hfrc_adjust_disable(void);
201 
202 #ifdef __cplusplus
203 }
204 #endif
205 
206 #endif // AM_HAL_CLKGEN_H
207