1 //***************************************************************************** 2 // 3 // am_hal_iom.h 4 //! @file 5 //! 6 //! @brief Functions for accessing and configuring the IO Master module 7 //! 8 //! @addtogroup iom2 IO Master (SPI/I2C) 9 //! @ingroup apollo2hal 10 //! @{ 11 12 //***************************************************************************** 13 14 //***************************************************************************** 15 // 16 // Copyright (c) 2017, Ambiq Micro 17 // All rights reserved. 18 // 19 // Redistribution and use in source and binary forms, with or without 20 // modification, are permitted provided that the following conditions are met: 21 // 22 // 1. Redistributions of source code must retain the above copyright notice, 23 // this list of conditions and the following disclaimer. 24 // 25 // 2. Redistributions in binary form must reproduce the above copyright 26 // notice, this list of conditions and the following disclaimer in the 27 // documentation and/or other materials provided with the distribution. 28 // 29 // 3. Neither the name of the copyright holder nor the names of its 30 // contributors may be used to endorse or promote products derived from this 31 // software without specific prior written permission. 32 // 33 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 34 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 37 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 38 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 39 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 40 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 41 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 43 // POSSIBILITY OF SUCH DAMAGE. 44 // 45 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 46 // 47 //***************************************************************************** 48 49 #ifndef AM_HAL_IOM_H 50 #define AM_HAL_IOM_H 51 52 //***************************************************************************** 53 // 54 // Macro definitions 55 // 56 //***************************************************************************** 57 58 //***************************************************************************** 59 // 60 //! @name IOM Clock Frequencies 61 //! @brief Macro definitions for common SPI and I2C clock frequencies. 62 //! 63 //! These macros may be used with the ui32ClockFrequency member of the 64 //! am_hal_iom_config_t structure to set the clock frequency of the serial 65 //! interfaces. 66 //! 67 //! This list of frequencies is not exhaustive by any means. If your desired 68 //! frequency is not in this list, simply set ui32ClockFrequency to the 69 //! desired frequency (in Hz) when calling am_hal_iom_config(). 70 // 71 //***************************************************************************** 72 #define AM_HAL_IOM_24MHZ 24000000 73 #define AM_HAL_IOM_16MHZ 16000000 74 #define AM_HAL_IOM_12MHZ 12000000 75 #define AM_HAL_IOM_8MHZ 8000000 76 #define AM_HAL_IOM_6MHZ 6000000 77 #define AM_HAL_IOM_4MHZ 4000000 78 #define AM_HAL_IOM_3MHZ 3000000 79 #define AM_HAL_IOM_2MHZ 2000000 80 #define AM_HAL_IOM_1_5MHZ 1500000 81 #define AM_HAL_IOM_1MHZ 1000000 82 #define AM_HAL_IOM_800KHZ 800000 83 #define AM_HAL_IOM_750KHZ 750000 84 #define AM_HAL_IOM_500KHZ 500000 85 #define AM_HAL_IOM_400KHZ 400000 86 #define AM_HAL_IOM_375KHZ 375000 87 #define AM_HAL_IOM_250KHZ 250000 88 #define AM_HAL_IOM_200KHZ 200000 89 #define AM_HAL_IOM_125KHZ 125000 90 #define AM_HAL_IOM_100KHZ 100000 91 #define AM_HAL_IOM_50KHZ 50000 92 #define AM_HAL_IOM_10KHZ 10000 93 94 // Hardware FIFO Size 95 #define AM_HAL_IOM_MAX_FIFO_SIZE 128 96 97 //***************************************************************************** 98 // 99 //! @name IOM Physical Protocols 100 //! @brief Macro Definitions for general IOM configuration. 101 //! 102 //! These macros may be used with the am_hal_iom_config_t structure to set the 103 //! operating parameters of each serial IO master module. Choose SPIMODE to 104 //! select the SPI interface, or I2CMODE to select the I2C interface. 105 //! 106 //! @{ 107 // 108 //***************************************************************************** 109 #define AM_HAL_IOM_SPIMODE AM_REG_IOMSTR_CFG_IFCSEL(1) 110 #define AM_HAL_IOM_I2CMODE AM_REG_IOMSTR_CFG_IFCSEL(0) 111 //! @} 112 113 //***************************************************************************** 114 // 115 //! @name IOM Operations 116 //! @brief Macro definitions used for ui32Operation parameters. 117 //! 118 //! These macros may be used to specify which action an IOM command will 119 //! execute. The 'OFFSET' operations will cause the IOM hardware to transmit the 120 //! provided 1-byte 'offset' before executing the rest of the command. 121 //! 122 //! @{ 123 // 124 //***************************************************************************** 125 #define AM_HAL_IOM_WRITE 0x00000000 126 #define AM_HAL_IOM_READ 0x80000000 127 //! @} 128 129 //***************************************************************************** 130 // 131 //! @name Command Options 132 //! @brief Macro definitions used for ui32Options parameters. 133 //! 134 //! These macros are all related to SPI or I2C command words. They can be used 135 //! to set specific options on a per-transaction basis. 136 //! 137 //! - CS_LOW - Do not raise the CS signal at the end of this SPI command. 138 //! - NO_STOP - Do not release the I2C bus with a STOP bit after this command. 139 //! - LSB_FIRST - Reverse the payload bits of this command. 140 //! - 10BIT_ADDRESS - (I2C only) use a 10-bit I2C address protocol. 141 //! - RAW - Don't use an offset byte. 142 //! - OFFSET() - Send this 1-byte offset as the first byte of the transaction. 143 //! This can be used to access "registers" in external I2C devices, or add a 144 //! 1-byte write to the beginning of a SPI write or read command. See 145 //! "normal mode" operation in the I2C/SPI Master section of the datasheet 146 //! for more information on this parameter. 147 //! 148 //! @{ 149 // 150 //***************************************************************************** 151 #define AM_HAL_IOM_CS_LOW 0x10000000 152 #define AM_HAL_IOM_NO_STOP 0x10000000 153 #define AM_HAL_IOM_LSB_FIRST 0x08000000 154 #define AM_HAL_IOM_10BIT_ADDRESS 0x04000000 155 #define AM_HAL_IOM_RAW 0x40000000 156 #define AM_HAL_IOM_OFFSET(n) (((n) << 8) & 0x0000FF00) 157 //! @} 158 159 //***************************************************************************** 160 // 161 //! @name IOM Interrupts 162 //! @brief Macro definitions for IOM interrupt status bits. 163 //! 164 //! These macros correspond to the bits in the IOM interrupt status register. 165 //! They may be used with any of the \e am_hal_iom_int_x() functions. 166 //! 167 //! @{ 168 // 169 //***************************************************************************** 170 #define AM_HAL_IOM_INT_ARB AM_REG_IOMSTR_INTEN_ARB_M 171 #define AM_HAL_IOM_INT_STOP AM_REG_IOMSTR_INTEN_STOP_M 172 #define AM_HAL_IOM_INT_START AM_REG_IOMSTR_INTEN_START_M 173 #define AM_HAL_IOM_INT_ICMD AM_REG_IOMSTR_INTEN_ICMD_M 174 #define AM_HAL_IOM_INT_IACC AM_REG_IOMSTR_INTEN_IACC_M 175 #define AM_HAL_IOM_INT_WTLEN AM_REG_IOMSTR_INTEN_WTLEN_M 176 #define AM_HAL_IOM_INT_NAK AM_REG_IOMSTR_INTEN_NAK_M 177 #define AM_HAL_IOM_INT_FOVFL AM_REG_IOMSTR_INTEN_FOVFL_M 178 #define AM_HAL_IOM_INT_FUNDFL AM_REG_IOMSTR_INTEN_FUNDFL_M 179 #define AM_HAL_IOM_INT_THR AM_REG_IOMSTR_INTEN_THR_M 180 #define AM_HAL_IOM_INT_CMDCMP AM_REG_IOMSTR_INTEN_CMDCMP_M 181 182 #define AM_HAL_IOM_INT_ALL ( \ 183 AM_HAL_IOM_INT_ARB | \ 184 AM_HAL_IOM_INT_STOP | \ 185 AM_HAL_IOM_INT_START | \ 186 AM_HAL_IOM_INT_ICMD | \ 187 AM_HAL_IOM_INT_IACC | \ 188 AM_HAL_IOM_INT_WTLEN | \ 189 AM_HAL_IOM_INT_NAK | \ 190 AM_HAL_IOM_INT_FOVFL | \ 191 AM_HAL_IOM_INT_FUNDFL | \ 192 AM_HAL_IOM_INT_THR | \ 193 AM_HAL_IOM_INT_CMDCMP) 194 195 #define AM_HAL_IOM_INT_SWERR ( \ 196 AM_HAL_IOM_INT_ICMD | \ 197 AM_HAL_IOM_INT_FOVFL | \ 198 AM_HAL_IOM_INT_FUNDFL | \ 199 AM_HAL_IOM_INT_IACC) 200 201 #define AM_HAL_IOM_INT_I2CARBERR ( \ 202 AM_HAL_IOM_INT_ARB | \ 203 AM_HAL_IOM_INT_START | \ 204 AM_HAL_IOM_INT_STOP) 205 //! @} 206 207 //***************************************************************************** 208 // 209 //! @name Software IOM modules 210 //! @brief Macro definitions for using the software I2C interface. 211 //! 212 //! Use this macro as the module number for standard IOM functions to emulate 213 //! them using the bit-banged i2c interface. 214 //! 215 //! @{ 216 // 217 //***************************************************************************** 218 #define AM_HAL_IOM_I2CBB_MODULE AM_REG_IOMSTR_NUM_MODULES 219 //! @} 220 221 //***************************************************************************** 222 // 223 //! @name IOM Return Codes 224 //! @brief Enum definitions for defining return values for IOM APIs 225 //! 226 //! This enum defines possible values for non-void IOM APIs 227 //! 228 //! @{ 229 // 230 //***************************************************************************** 231 typedef enum 232 { 233 AM_HAL_IOM_SUCCESS = 0, 234 AM_HAL_IOM_ERR_TIMEOUT, 235 AM_HAL_IOM_ERR_INVALID_MODULE, 236 AM_HAL_IOM_ERR_INVALID_PARAM, 237 AM_HAL_IOM_ERR_INVALID_CFG, 238 AM_HAL_IOM_ERR_INVALID_OPER, 239 AM_HAL_IOM_ERR_I2C_NAK, 240 AM_HAL_IOM_ERR_I2C_ARB, 241 AM_HAL_IOM_ERR_RESOURCE_ERR, 242 } am_hal_iom_status_e ; 243 244 //! @} 245 246 //***************************************************************************** 247 // 248 //! @brief Union type for a word-aligned, byte-addressable array. 249 //! 250 //! This is a convenience macro that may be used to define byte-addressable 251 //! arrays with 32-bit alignment. This allows the programmer to define SPI or 252 //! I2C transactions as a series of 8-bit values, but also write them to the 253 //! IOM FIFO efficiently as a series of 32-bit values. 254 //! 255 //! Example usage: 256 //! 257 //! @code 258 //! // 259 //! // Declare a buffer array with at least 3-bytes worth of space. 260 //! // 261 //! am_hal_iom_buffer(3) sBuffer; 262 //! 263 //! // 264 //! // Populate the buffer with a 3-byte command. 265 //! // 266 //! sBuffer.bytes[0] = 's'; 267 //! sBuffer.bytes[1] = 'p'; 268 //! sBuffer.bytes[2] = 'i'; 269 //! 270 //! // 271 //! // Send the buffer over the spi interface. 272 //! // 273 //! am_hal_iom_spi_write(psDevice, sBuffer.words, 3, 0); 274 //! 275 //! @endcode 276 // 277 //***************************************************************************** 278 #define am_hal_iom_buffer(A) \ 279 union \ 280 { \ 281 uint32_t words[(A + 3) >> 2]; \ 282 uint8_t bytes[A]; \ 283 } 284 285 //***************************************************************************** 286 // 287 //! @brief Configuration structure for the IO master module. 288 // 289 //***************************************************************************** 290 typedef struct 291 { 292 // 293 //! @brief Selects the physical protocol for the IO master module. Choose 294 //! either AM_HAL_IOM_SPIMODE or AM_HAL_IOM_I2CMODE. 295 // 296 uint32_t ui32InterfaceMode; 297 298 // 299 //! @brief Selects the output clock frequency for SPI or I2C mode. Choose 300 //! one of the AM_HAL_IOM_nMHZ or AM_HAL_IOM_nKHZ macros. 301 // 302 uint32_t ui32ClockFrequency; 303 304 // 305 //! Select the SPI clock phase (unused in I2C mode). 306 // 307 bool bSPHA; 308 309 // 310 //! Select the SPI clock polarity (unused in I2C mode). 311 // 312 bool bSPOL; 313 314 // 315 //! @brief Select the FIFO write threshold. 316 //! 317 //! The IOM controller will generate a processor interrupt when the number 318 //! of entries in the FIFO goes *below* this number. 319 // 320 uint8_t ui8WriteThreshold; 321 322 // 323 //! @brief Select the FIFO read threshold. 324 //! 325 //! The IOM controller will generate a processor interrupt when the number 326 //! of entries in the FIFO grows *larger* than this number. 327 // 328 uint8_t ui8ReadThreshold; 329 330 } 331 am_hal_iom_config_t; 332 333 //***************************************************************************** 334 // 335 //! Configuration structure for an individual SPI device. 336 // 337 //***************************************************************************** 338 typedef struct 339 { 340 // 341 //! IOM module to use for communicating with this device. 342 // 343 uint32_t ui32Module; 344 345 // 346 //! Chip select signal that should be used for this device. 347 // 348 uint32_t ui32ChipSelect; 349 350 // 351 //! Additional options that will ALWAYS be ORed into the command word. 352 // 353 uint32_t ui32Options; 354 } 355 am_hal_iom_spi_device_t; 356 357 //***************************************************************************** 358 // 359 //! Configuration structure for an individual I2C device. 360 // 361 //***************************************************************************** 362 typedef struct 363 { 364 // 365 //! IOM module to use for communicating with this device. 366 // 367 uint32_t ui32Module; 368 369 // 370 //! I2C address associated with this device. 371 // 372 uint32_t ui32BusAddress; 373 374 // 375 //! Additional options that will ALWAYS be ORed into the command word. 376 // 377 uint32_t ui32Options; 378 } 379 am_hal_iom_i2c_device_t; 380 381 //***************************************************************************** 382 // 383 // Typedef for non-blocking function callbacks. 384 // 385 //***************************************************************************** 386 typedef void (*am_hal_iom_callback_t)(void); 387 388 //***************************************************************************** 389 // 390 // Typedef for a function that waits until the IOM queue is empty. 391 // 392 //***************************************************************************** 393 typedef void (*am_hal_iom_queue_flush_t)(uint32_t); 394 395 extern am_hal_iom_queue_flush_t am_hal_iom_queue_flush; 396 397 398 //***************************************************************************** 399 // 400 // Operations 401 // 402 //***************************************************************************** 403 #define AM_HAL_IOM_QUEUE_SPI_WRITE 0 404 #define AM_HAL_IOM_QUEUE_SPI_READ 1 405 #define AM_HAL_IOM_QUEUE_I2C_WRITE 2 406 #define AM_HAL_IOM_QUEUE_I2C_READ 3 407 408 //***************************************************************************** 409 // 410 // Structure to hold IOM operations. 411 // 412 //***************************************************************************** 413 typedef struct 414 { 415 uint32_t ui32Operation; 416 uint32_t ui32Module; 417 uint32_t ui32ChipSelect; 418 uint32_t *pui32Data; 419 uint32_t ui32NumBytes; 420 uint32_t ui32Options; 421 am_hal_iom_callback_t pfnCallback; 422 } 423 am_hal_iom_queue_entry_t; 424 425 //***************************************************************************** 426 // 427 // Structure to hold IOM configuration during module power-down. 428 // 429 //***************************************************************************** 430 typedef struct 431 { 432 uint32_t FIFOTHR; 433 uint32_t CLKCFG; 434 uint32_t CFG; 435 uint32_t INTEN; 436 uint32_t bValid; 437 } 438 am_hal_iom_pwrsave_t; 439 440 //***************************************************************************** 441 // 442 // Global variables 443 // 444 //***************************************************************************** 445 extern am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES]; 446 447 #ifdef __cplusplus 448 extern "C" 449 { 450 #endif 451 452 //***************************************************************************** 453 // 454 // External function definitions 455 // 456 //***************************************************************************** 457 extern void am_hal_iom_pwrctrl_enable(uint32_t ui32Module); 458 extern void am_hal_iom_pwrctrl_disable(uint32_t ui32Module); 459 extern void am_hal_iom_power_on_restore(uint32_t ui32Module); 460 extern void am_hal_iom_power_off_save(uint32_t ui32Module); 461 extern void am_hal_iom_config(uint32_t ui32Module, 462 const am_hal_iom_config_t *psConfig); 463 extern uint32_t am_hal_iom_frequency_get(uint32_t ui32Module); 464 extern void am_hal_iom_enable(uint32_t ui32Module); 465 extern void am_hal_iom_disable(uint32_t ui32Module); 466 extern am_hal_iom_status_e am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, 467 uint32_t *pui32Data, uint32_t ui32NumBytes, 468 uint32_t ui32Options); 469 extern am_hal_iom_status_e am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, 470 uint32_t *pui32Data, uint32_t ui32NumBytes, 471 uint32_t ui32Options); 472 extern am_hal_iom_status_e am_hal_iom_spi_fullduplex(uint32_t ui32Module, uint32_t ui32ChipSelect, 473 uint32_t *pui32TxData, uint32_t *pui32RxData, 474 uint32_t ui32NumBytes, uint32_t ui32Options); 475 476 extern am_hal_iom_status_e am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, 477 uint32_t *pui32Data, uint32_t ui32NumBytes, 478 uint32_t ui32Options); 479 extern am_hal_iom_status_e am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, 480 uint32_t *pui32Data, uint32_t ui32NumBytes, 481 uint32_t ui32Options); 482 extern am_hal_iom_status_e am_hal_iom_spi_fullduplex_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, 483 uint32_t *pui32TxData, uint32_t *pui32RxData, 484 uint32_t ui32NumBytes, uint32_t ui32Options); 485 extern am_hal_iom_status_e am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, 486 uint32_t *pui32Data, uint32_t ui32NumBytes, 487 uint32_t ui32Options, 488 am_hal_iom_callback_t pfnCallback); 489 extern am_hal_iom_status_e am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, 490 uint32_t *pui32Data, uint32_t ui32NumBytes, 491 uint32_t ui32Options, 492 am_hal_iom_callback_t pfnCallback); 493 extern void am_hal_iom_spi_cmd_run(uint32_t ui32Operation, 494 uint32_t ui32Module, 495 uint32_t ui32ChipSelect, 496 uint32_t ui32NumBytes, 497 uint32_t ui32Options); 498 extern am_hal_iom_status_e am_hal_iom_i2c_write(uint32_t ui32Module, 499 uint32_t ui32BusAddress, 500 uint32_t *pui32Data, 501 uint32_t ui32NumBytes, 502 uint32_t ui32Options); 503 extern am_hal_iom_status_e am_hal_iom_i2c_read(uint32_t ui32Module, 504 uint32_t ui32BusAddress, 505 uint32_t *pui32Data, 506 uint32_t ui32NumBytes, 507 uint32_t ui32Options); 508 extern am_hal_iom_status_e am_hal_iom_i2c_write_nq(uint32_t ui32Module, 509 uint32_t ui32BusAddress, 510 uint32_t *pui32Data, 511 uint32_t ui32NumBytes, 512 uint32_t ui32Options); 513 extern am_hal_iom_status_e am_hal_iom_i2c_read_nq(uint32_t ui32Module, 514 uint32_t ui32BusAddress, 515 uint32_t *pui32Data, 516 uint32_t ui32NumBytes, 517 uint32_t ui32Options); 518 extern am_hal_iom_status_e am_hal_iom_i2c_write_nb(uint32_t ui32Module, 519 uint32_t ui32BusAddress, 520 uint32_t *pui32Data, 521 uint32_t ui32NumBytes, 522 uint32_t ui32Options, 523 am_hal_iom_callback_t pfnCallback); 524 extern am_hal_iom_status_e am_hal_iom_i2c_read_nb(uint32_t ui32Module, 525 uint32_t ui32BusAddress, 526 uint32_t *pui32Data, 527 uint32_t ui32NumBytes, 528 uint32_t ui32Options, 529 am_hal_iom_callback_t pfnCallback); 530 extern am_hal_iom_status_e am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, 531 uint32_t ui32Module, 532 uint32_t ui32BusAddress, 533 uint32_t ui32NumBytes, 534 uint32_t ui32Options); 535 extern void am_hal_iom_command_repeat_set(uint32_t ui32Module, 536 uint32_t ui32CmdCount); 537 extern uint32_t am_hal_iom_status_get(uint32_t ui32Module); 538 extern am_hal_iom_status_e am_hal_iom_error_status_get(uint32_t ui32Module); 539 extern uint32_t am_hal_iom_fifo_write(uint32_t ui32Module, uint32_t *pui32Data, 540 uint32_t ui32NumBytes); 541 extern uint32_t am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data, 542 uint32_t ui32NumBytes); 543 extern uint8_t am_hal_iom_fifo_empty_slots(uint32_t ui32Module); 544 extern uint8_t am_hal_iom_fifo_full_slots(uint32_t ui32Module); 545 extern void am_hal_iom_poll_complete(uint32_t ui32Module); 546 extern void am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status); 547 extern void am_hal_iom_int_enable(uint32_t ui32Module, uint32_t ui32Interrupt); 548 extern uint32_t am_hal_iom_int_enable_get(uint32_t ui32Module); 549 extern void am_hal_iom_int_disable(uint32_t ui32Module, uint32_t ui32Interrupt); 550 extern void am_hal_iom_int_clear(uint32_t ui32Module, uint32_t ui32Interrupt); 551 extern void am_hal_iom_int_set(uint32_t ui32Module, uint32_t ui32Interrupt); 552 extern uint32_t am_hal_iom_int_status_get(uint32_t ui32Module, bool bEnabledOnly); 553 extern void am_hal_iom_queue_init(uint32_t ui32ModuleNum, 554 am_hal_iom_queue_entry_t *psQueueMemory, 555 uint32_t ui32QueueMemSize); 556 extern uint32_t am_hal_iom_queue_length_get(uint32_t ui32Module); 557 extern void am_hal_iom_sleeping_queue_flush(uint32_t ui32Module); 558 extern am_hal_iom_status_e am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, 559 uint32_t *pui32Data, uint32_t ui32NumBytes, 560 uint32_t ui32Options, 561 am_hal_iom_callback_t pfnCallback); 562 extern am_hal_iom_status_e am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, 563 uint32_t *pui32Data, uint32_t ui32NumBytes, 564 uint32_t ui32Options, 565 am_hal_iom_callback_t pfnCallback); 566 extern am_hal_iom_status_e am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, 567 uint32_t *pui32Data, uint32_t ui32NumBytes, 568 uint32_t ui32Options, 569 am_hal_iom_callback_t pfnCallback); 570 extern am_hal_iom_status_e am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, 571 uint32_t *pui32Data, uint32_t ui32NumBytes, 572 uint32_t ui32Options, 573 am_hal_iom_callback_t pfnCallback); 574 extern void am_hal_iom_queue_start_next_msg(uint32_t ui32Module); 575 extern void am_hal_iom_queue_service(uint32_t ui32Module, uint32_t ui32Status); 576 577 //***************************************************************************** 578 // 579 // Helper functions. 580 // 581 //***************************************************************************** 582 #define AM_IOMASTER_ISR_QUEUE(x) \ 583 void am_iomaster##x##_isr(void) \ 584 { \ 585 uint32_t ui32IntStatus; \ 586 ui32IntStatus = am_hal_iom_int_status_get(x, false); \ 587 am_hal_iom_int_clear(x, ui32IntStatus); \ 588 am_hal_iom_queue_service(x, ui32IntStatus); \ 589 } 590 591 #define AM_IOMASTER_ISR_NB(x) \ 592 void am_iomaster##x##_isr(void) \ 593 { \ 594 uint32_t ui32IntStatus; \ 595 ui32IntStatus = am_hal_iom_int_status_get(x, false); \ 596 am_hal_iom_int_clear(x, ui32IntStatus); \ 597 am_hal_iom_int_service(x, ui32IntStatus); \ 598 } 599 600 #ifdef __cplusplus 601 } 602 #endif 603 604 #endif // AM_HAL_IOM_H 605 606 //***************************************************************************** 607 // 608 // End Doxygen group. 609 //! @} 610 // 611 //***************************************************************************** 612