1 //***************************************************************************** 2 // 3 // am_hal_pwrctrl.h 4 //! @file 5 //! 6 //! @brief Functions for enabling and disabling power domains. 7 //! 8 //! @addtogroup pwrctrl2 Power Control 9 //! @ingroup apollo2hal 10 //! @{ 11 12 //***************************************************************************** 13 14 //***************************************************************************** 15 // 16 // Copyright (c) 2017, Ambiq Micro 17 // All rights reserved. 18 // 19 // Redistribution and use in source and binary forms, with or without 20 // modification, are permitted provided that the following conditions are met: 21 // 22 // 1. Redistributions of source code must retain the above copyright notice, 23 // this list of conditions and the following disclaimer. 24 // 25 // 2. Redistributions in binary form must reproduce the above copyright 26 // notice, this list of conditions and the following disclaimer in the 27 // documentation and/or other materials provided with the distribution. 28 // 29 // 3. Neither the name of the copyright holder nor the names of its 30 // contributors may be used to endorse or promote products derived from this 31 // software without specific prior written permission. 32 // 33 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 34 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 37 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 38 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 39 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 40 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 41 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 43 // POSSIBILITY OF SUCH DAMAGE. 44 // 45 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 46 // 47 //***************************************************************************** 48 49 #ifndef AM_HAL_PWRCTRL_H 50 #define AM_HAL_PWRCTRL_H 51 52 //***************************************************************************** 53 // 54 // Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable() 55 // 56 //***************************************************************************** 57 #define AM_HAL_PWRCTRL_ADC AM_REG_PWRCTRL_DEVICEEN_ADC_EN 58 #define AM_HAL_PWRCTRL_IOM0 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN 59 #define AM_HAL_PWRCTRL_IOM1 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN 60 #define AM_HAL_PWRCTRL_IOM2 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN 61 #define AM_HAL_PWRCTRL_IOM3 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN 62 #define AM_HAL_PWRCTRL_IOM4 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN 63 #define AM_HAL_PWRCTRL_IOM5 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN 64 #define AM_HAL_PWRCTRL_IOS AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN 65 #define AM_HAL_PWRCTRL_PDM AM_REG_PWRCTRL_DEVICEEN_PDM_EN 66 #define AM_HAL_PWRCTRL_UART0 AM_REG_PWRCTRL_DEVICEEN_UART0_EN 67 #define AM_HAL_PWRCTRL_UART1 AM_REG_PWRCTRL_DEVICEEN_UART1_EN 68 69 //***************************************************************************** 70 // 71 // Macro to set the appropriate IOM peripheral when using 72 // am_hal_pwrctrl_periph_enable()/disable(). 73 // For Apollo2, the module argument must resolve to be a value from 0-5. 74 // 75 //***************************************************************************** 76 #define AM_HAL_PWRCTRL_IOM(module) \ 77 (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN << module) 78 79 //***************************************************************************** 80 // 81 // Macro to set the appropriate UART peripheral when using 82 // am_hal_pwrctrl_periph_enable()/disable(). 83 // For Apollo2, the module argument must resolve to be a value from 0-1. 84 // 85 //***************************************************************************** 86 #define AM_HAL_PWRCTRL_UART(module) \ 87 (AM_REG_PWRCTRL_DEVICEEN_UART0_EN << module) 88 89 90 //***************************************************************************** 91 // 92 // Memory enable values for am_hal_pwrctrl_memory_enable() 93 // 94 //***************************************************************************** 95 #define AM_HAL_PWRCTRL_MEMEN_SRAM8K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K 96 #define AM_HAL_PWRCTRL_MEMEN_SRAM16K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K 97 #define AM_HAL_PWRCTRL_MEMEN_SRAM24K (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K | \ 98 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2) 99 #define AM_HAL_PWRCTRL_MEMEN_SRAM32K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K 100 #define AM_HAL_PWRCTRL_MEMEN_SRAM64K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K 101 #define AM_HAL_PWRCTRL_MEMEN_SRAM96K \ 102 (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K | \ 103 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP2) 104 #define AM_HAL_PWRCTRL_MEMEN_SRAM128K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K 105 #define AM_HAL_PWRCTRL_MEMEN_SRAM160K \ 106 (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K | \ 107 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4) 108 #define AM_HAL_PWRCTRL_MEMEN_SRAM192K \ 109 (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K | \ 110 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4 | \ 111 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5) 112 #define AM_HAL_PWRCTRL_MEMEN_SRAM224K \ 113 (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K | \ 114 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4 | \ 115 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5 | \ 116 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP6) 117 #define AM_HAL_PWRCTRL_MEMEN_SRAM256K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K 118 119 #define AM_HAL_PWRCTRL_MEMEN_FLASH512K AM_REG_PWRCTRL_MEMEN_FLASH0_EN 120 #define AM_HAL_PWRCTRL_MEMEN_FLASH1M \ 121 (AM_REG_PWRCTRL_MEMEN_FLASH0_EN | \ 122 AM_REG_PWRCTRL_MEMEN_FLASH1_EN) 123 #define AM_HAL_PWRCTRL_MEMEN_CACHE \ 124 (AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | \ 125 AM_REG_PWRCTRL_MEMEN_CACHEB2_EN) 126 #define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS \ 127 ~(AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | \ 128 AM_REG_PWRCTRL_MEMEN_CACHEB2_EN) 129 130 // 131 // Power up all available memory devices (this is the default power up state) 132 // 133 #define AM_HAL_PWRCTRL_MEMEN_ALL \ 134 (AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL | \ 135 AM_REG_PWRCTRL_MEMEN_FLASH0_EN | \ 136 AM_REG_PWRCTRL_MEMEN_FLASH1_EN | \ 137 AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | \ 138 AM_REG_PWRCTRL_MEMEN_CACHEB2_EN) 139 140 //***************************************************************************** 141 // 142 // Peripheral power enable and disable delays 143 // The delay counts are based on an internal clock that runs at half of 144 // HFRC. Therefore, we need to double the delay cycles. 145 // 146 //***************************************************************************** 147 #define AM_HAL_PWRCTRL_DEVICEEN_DELAYCYCLES (22 * 2) 148 #define AM_HAL_PWRCTRL_DEVICEDIS_DELAYCYCLES (22 * 2) 149 150 // 151 // Use the following only when enabling after sleep (not during initialization). 152 // 153 #define AM_HAL_PWRCTRL_BUCKEN_DELAYCYCLES (0 * 2) 154 #define AM_HAL_PWRCTRL_BUCKDIS_DELAYCYCLES (15 * 2) 155 156 //***************************************************************************** 157 // 158 // Peripheral PWRONSTATUS groupings. 159 // 160 //***************************************************************************** 161 // 162 // Group DEVICEEN bits (per PWRONSTATUS groupings). 163 // 164 #define AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2 \ 165 (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN | \ 166 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN | \ 167 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN ) 168 169 #define AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5 \ 170 (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN | \ 171 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN | \ 172 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN ) 173 174 #define AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS \ 175 (AM_REG_PWRCTRL_DEVICEEN_UART0_EN | \ 176 AM_REG_PWRCTRL_DEVICEEN_UART1_EN | \ 177 AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN ) 178 179 #define AM_HAL_PWRCTRL_DEVICEEN_ADC AM_REG_PWRCTRL_DEVICEEN_ADC_EN 180 #define AM_HAL_PWRCTRL_DEVICEEN_PDM AM_REG_PWRCTRL_DEVICEEN_PDM_EN 181 182 // 183 // Map PWRONSTATUS bits to peripheral groupings. 184 // 185 #define AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS AM_REG_PWRCTRL_PWRONSTATUS_PDA_M 186 #define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5 AM_REG_PWRCTRL_PWRONSTATUS_PDC_M 187 #define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2 AM_REG_PWRCTRL_PWRONSTATUS_PDB_M 188 #define AM_HAL_PWRCTRL_PWRONSTATUS_ADC AM_REG_PWRCTRL_PWRONSTATUS_PDADC_M 189 #define AM_HAL_PWRCTRL_PWRONSTATUS_PDM AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_M 190 191 #define POLL_PWRSTATUS(ui32Peripheral) \ 192 if ( 1 ) \ 193 { \ 194 uint32_t ui32PwrOnStat; \ 195 if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2 ) \ 196 { \ 197 ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2; \ 198 } \ 199 else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5 ) \ 200 { \ 201 ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5; \ 202 } \ 203 else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS ) \ 204 { \ 205 ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS; \ 206 } \ 207 else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_ADC ) \ 208 { \ 209 ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_ADC; \ 210 } \ 211 else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_PDM ) \ 212 { \ 213 ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_PDM; \ 214 } \ 215 else \ 216 { \ 217 ui32PwrOnStat = 0xFFFFFFFF; \ 218 } \ 219 \ 220 /* */ \ 221 /* Wait for the power control setting to take effect. */ \ 222 /* */ \ 223 while ( !(AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrOnStat) ); \ 224 } 225 226 //***************************************************************************** 227 // 228 // Memory PWRONSTATUS enable values for am_hal_pwrctrl_memory_enable() 229 // 230 //***************************************************************************** 231 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K \ 232 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M 233 234 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K \ 235 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 236 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 237 238 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K \ 239 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ 240 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 241 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 242 243 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K \ 244 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ 245 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ 246 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 247 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 248 249 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K \ 250 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ 251 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ 252 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ 253 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 254 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 255 256 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K \ 257 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ 258 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ 259 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ 260 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ 261 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 262 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 263 264 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K \ 265 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ 266 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ 267 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ 268 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ 269 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ 270 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 271 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 272 273 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K \ 274 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \ 275 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ 276 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ 277 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ 278 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ 279 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ 280 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 281 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 282 283 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K \ 284 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M | \ 285 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \ 286 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ 287 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ 288 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ 289 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ 290 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ 291 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 292 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 293 294 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K \ 295 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M | \ 296 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M | \ 297 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \ 298 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ 299 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ 300 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ 301 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ 302 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ 303 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 304 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 305 306 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K \ 307 (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_M | \ 308 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M | \ 309 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M | \ 310 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \ 311 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \ 312 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \ 313 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \ 314 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \ 315 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \ 316 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \ 317 AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M) 318 319 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \ 320 AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K 321 322 #ifdef __cplusplus 323 extern "C" 324 { 325 #endif 326 327 //***************************************************************************** 328 // 329 // Function prototypes 330 // 331 //***************************************************************************** 332 extern void am_hal_pwrctrl_periph_enable(uint32_t ui32Peripheral); 333 extern void am_hal_pwrctrl_periph_disable(uint32_t ui32Peripheral); 334 extern bool am_hal_pwrctrl_memory_enable(uint32_t ui32MemEn); 335 extern void am_hal_pwrctrl_bucks_init(void); 336 extern void am_hal_pwrctrl_bucks_enable(void); 337 extern void am_hal_pwrctrl_bucks_disable(void); 338 extern void am_hal_pwrctrl_low_power_init(void); 339 340 #ifdef __cplusplus 341 } 342 #endif 343 344 #endif // AM_HAL_PWRCTRL_H 345 346 //***************************************************************************** 347 // 348 // End Doxygen group. 349 //! @} 350 // 351 //***************************************************************************** 352