1 //*****************************************************************************
2 //
3 // am_hal_reset.c
4 //! @file
5 //!
6 //! @brief Hardware abstraction layer for the Reset Generator module.
7 //!
8 //! @addtogroup rstgen2 Reset Generator (RSTGEN)
9 //! @ingroup apollo2hal
10 //! @{
11 //
12 //*****************************************************************************
13
14 //*****************************************************************************
15 //
16 // Copyright (c) 2017, Ambiq Micro
17 // All rights reserved.
18 //
19 // Redistribution and use in source and binary forms, with or without
20 // modification, are permitted provided that the following conditions are met:
21 //
22 // 1. Redistributions of source code must retain the above copyright notice,
23 // this list of conditions and the following disclaimer.
24 //
25 // 2. Redistributions in binary form must reproduce the above copyright
26 // notice, this list of conditions and the following disclaimer in the
27 // documentation and/or other materials provided with the distribution.
28 //
29 // 3. Neither the name of the copyright holder nor the names of its
30 // contributors may be used to endorse or promote products derived from this
31 // software without specific prior written permission.
32 //
33 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
37 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
40 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
41 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 // POSSIBILITY OF SUCH DAMAGE.
44 //
45 // This is part of revision 1.2.11 of the AmbiqSuite Development Package.
46 //
47 //*****************************************************************************
48
49 #include "am_mcu_apollo.h"
50
51 //*****************************************************************************
52 //
53 //! @brief Configure the Reset Generator.
54 //!
55 //! @param ui32Config - Or together the supplied macros to enable
56 //! configurations to obtain the desired reset generator settings.
57 //!
58 //! This function will set the reset generator's configuration register based on
59 //! the user's desired settings listed in the supplied arugment.
60 //!
61 //! @return None.
62 //
63 //*****************************************************************************
64 void
am_hal_reset_init(uint32_t ui32Config)65 am_hal_reset_init(uint32_t ui32Config)
66 {
67 //
68 // Write the configuration to the reset generator
69 //
70 AM_REG(RSTGEN, CFG) = ui32Config;
71 }
72
73 //*****************************************************************************
74 //
75 //! @brief Issue a POR (Apollo's last stage interrupt).
76 //!
77 //! This function will issue a POR reset.
78 //! The Apollo chip has numerous stages of reset. POR is the last and is also
79 //! the reset invoked by the chip's reset pin, the watchdog timer, the AIRCR
80 //! reset, and the SWD debugger requested interrupt.
81 //!
82 //! The Debug Access Port in the M4 is not cleared by this reset.
83 //!
84 //! @return None.
85 //
86 //*****************************************************************************
am_hal_reset_por(void)87 void am_hal_reset_por(void)
88 {
89 //
90 // Write the POR key to the software POR register.
91 //
92 AM_REG(RSTGEN, SWPOR) =
93 AM_REG_RSTGEN_SWPOR_SWPORKEY(AM_REG_RSTGEN_SWPOR_SWPORKEY_KEYVALUE);
94 }
95
96 //*****************************************************************************
97 //
98 //! @brief Issue a POI (Apollo's second stage interrupt).
99 //!
100 //! This function will issue a POI reset.
101 //! The Apollo chip has numerous stages of reset. POI is the second stage.
102 //! A few modules are reset by POI that are not reset by POR, notably POI
103 //! causes the shadow registers to be reloaded from the OTP. A full power
104 //! cycle or POI should be used after writing new flash, debug or SRAM
105 //! protection bits into the OTP for these protections to take effect.
106 //!
107 //! The Debug Access Port in the M4 is not cleared by this reset.
108 //!
109 //! @return None.
110 //
111 //*****************************************************************************
am_hal_reset_poi(void)112 void am_hal_reset_poi(void)
113 {
114 //
115 // Write the POI key to the software POI register.
116 //
117 AM_REG(RSTGEN, SWPOI) =
118 AM_REG_RSTGEN_SWPOI_SWPOIKEY(AM_REG_RSTGEN_SWPOI_SWPOIKEY_KEYVALUE);
119 }
120
121 //*****************************************************************************
122 //
123 //! @brief Retrieve the status bits from the reset generator.
124 //!
125 //! This function will get the status bits from the reset generator.
126 //! These bits are sticky and show the accumulation of reset types that the
127 //! Apollo chip has experienced since power on. One should clear these out
128 //! after reading them.
129 //!
130 //! @return None.
131 //
132 //*****************************************************************************
am_hal_reset_status_get(void)133 uint32_t am_hal_reset_status_get(void)
134 {
135 //
136 // Retrieve the reset generator status bits
137 //
138 return AM_REG(RSTGEN, STAT);
139 }
140
141 //*****************************************************************************
142 //
143 //! @brief Clear ALL of the status bits in the reset generator.
144 //!
145 //! This function will clear all status bits in the reset generator status.
146 //!
147 //! @return None.
148 //
149 //*****************************************************************************
am_hal_reset_status_clear(void)150 void am_hal_reset_status_clear(void)
151 {
152 AM_REG(RSTGEN, CLRSTAT) = AM_REG_RSTGEN_CLRSTAT_CLRSTAT(1);
153 }
154
155 //*****************************************************************************
156 //
157 // End Doxygen group.
158 //! @}
159 //
160 //*****************************************************************************
161