1 //***************************************************************************** 2 // 3 // am_reg_cachectrl.h 4 //! @file 5 //! 6 //! @brief Register macros for the CACHECTRL module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_CACHECTRL_H 45 #define AM_REG_CACHECTRL_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_CACHECTRL_NUM_MODULES 1 53 #define AM_REG_CACHECTRLn(n) \ 54 (REG_CACHECTRL_BASEADDR + 0x00001000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_CACHECTRL_CACHECFG_O 0x00000000 62 #define AM_REG_CACHECTRL_FLASHCFG_O 0x00000004 63 #define AM_REG_CACHECTRL_CACHECTRL_O 0x00000008 64 #define AM_REG_CACHECTRL_NCR0START_O 0x00000010 65 #define AM_REG_CACHECTRL_NCR0END_O 0x00000014 66 #define AM_REG_CACHECTRL_NCR1START_O 0x00000018 67 #define AM_REG_CACHECTRL_NCR1END_O 0x0000001C 68 #define AM_REG_CACHECTRL_CACHEMODE_O 0x00000030 69 #define AM_REG_CACHECTRL_DMON0_O 0x00000040 70 #define AM_REG_CACHECTRL_DMON1_O 0x00000044 71 #define AM_REG_CACHECTRL_DMON2_O 0x00000048 72 #define AM_REG_CACHECTRL_DMON3_O 0x0000004C 73 #define AM_REG_CACHECTRL_IMON0_O 0x00000050 74 #define AM_REG_CACHECTRL_IMON1_O 0x00000054 75 #define AM_REG_CACHECTRL_IMON2_O 0x00000058 76 #define AM_REG_CACHECTRL_IMON3_O 0x0000005C 77 78 //***************************************************************************** 79 // 80 // CACHECTRL_CACHECFG - Flash Cache Control Register 81 // 82 //***************************************************************************** 83 // Enable Cache Monitoring Stats. Only enable this for debug/performance 84 // analysis since it will consume additional power. See IMON/DMON registers for 85 // data. 86 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_S 24 87 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M 0x01000000 88 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(n) (((uint32_t)(n) << 24) & 0x01000000) 89 90 // Enable clock gating of entire cache data array subsystem. This should be 91 // enabled for normal operation. 92 #define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_S 20 93 #define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M 0x00100000 94 #define AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(n) (((uint32_t)(n) << 20) & 0x00100000) 95 96 // Unused. Should be left at default value. 97 #define AM_REG_CACHECTRL_CACHECFG_SMDLY_S 16 98 #define AM_REG_CACHECTRL_CACHECFG_SMDLY_M 0x000F0000 99 #define AM_REG_CACHECTRL_CACHECFG_SMDLY(n) (((uint32_t)(n) << 16) & 0x000F0000) 100 101 // Unused. Should be left at default value. 102 #define AM_REG_CACHECTRL_CACHECFG_DLY_S 12 103 #define AM_REG_CACHECTRL_CACHECFG_DLY_M 0x0000F000 104 #define AM_REG_CACHECTRL_CACHECFG_DLY(n) (((uint32_t)(n) << 12) & 0x0000F000) 105 106 // Enable LS (light sleep) of cache RAMs. This should not be enabled for normal 107 // operation. When this bit is set, the cache's RAMS will be put into light 108 // sleep mode while inactive. NOTE: if the cache is actively used, this may 109 // have an adverse affect on power since entering/exiting LS mode may consume 110 // more power than would be saved. 111 #define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_S 11 112 #define AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M 0x00000800 113 #define AM_REG_CACHECTRL_CACHECFG_CACHE_LS(n) (((uint32_t)(n) << 11) & 0x00000800) 114 115 // Enable clock gating of individual cache RAMs. This bit should be enabled for 116 // normal operation for lowest power consumption. 117 #define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_S 10 118 #define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M 0x00000400 119 #define AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE(n) (((uint32_t)(n) << 10) & 0x00000400) 120 121 // Enable Flash Data Caching. When set to 1, all instruction accesses to flash 122 // will be cached. 123 #define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_S 9 124 #define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M 0x00000200 125 #define AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(n) (((uint32_t)(n) << 9) & 0x00000200) 126 127 // Enable Flash Instruction Caching. When set to 1, all instruction accesses to 128 // flash will be cached. 129 #define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_S 8 130 #define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M 0x00000100 131 #define AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(n) (((uint32_t)(n) << 8) & 0x00000100) 132 133 // Bitfield should always be programmed to 0. 134 #define AM_REG_CACHECTRL_CACHECFG_SERIAL_S 7 135 #define AM_REG_CACHECTRL_CACHECFG_SERIAL_M 0x00000080 136 #define AM_REG_CACHECTRL_CACHECFG_SERIAL(n) (((uint32_t)(n) << 7) & 0x00000080) 137 138 // Sets the cache configuration. Only a single configuration of 0x5 is valid. 139 #define AM_REG_CACHECTRL_CACHECFG_CONFIG_S 4 140 #define AM_REG_CACHECTRL_CACHECFG_CONFIG_M 0x00000070 141 #define AM_REG_CACHECTRL_CACHECFG_CONFIG(n) (((uint32_t)(n) << 4) & 0x00000070) 142 #define AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E 0x00000050 143 144 // Enable Non-cacheable region 1. See the NCR1 registers to set the region 145 // boundaries and size. 146 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_S 3 147 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M 0x00000008 148 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1(n) (((uint32_t)(n) << 3) & 0x00000008) 149 150 // Enable Non-cacheable region 0. See the NCR0 registers to set the region 151 // boundaries and size. 152 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_S 2 153 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M 0x00000004 154 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0(n) (((uint32_t)(n) << 2) & 0x00000004) 155 156 // Sets the cache replacement policy. 0=LRR (least recently replaced), 1=LRU 157 // (least recently used). LRR minimizes writes to the TAG SRAM and is 158 // recommended. 159 #define AM_REG_CACHECTRL_CACHECFG_LRU_S 1 160 #define AM_REG_CACHECTRL_CACHECFG_LRU_M 0x00000002 161 #define AM_REG_CACHECTRL_CACHECFG_LRU(n) (((uint32_t)(n) << 1) & 0x00000002) 162 163 // Enables the main flash cache controller logic and enables power to the cache 164 // RAMs. Instruction and Data caching need to be enabled independently using 165 // the ICACHE_ENABLE and DCACHE_ENABLE bits. 166 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_S 0 167 #define AM_REG_CACHECTRL_CACHECFG_ENABLE_M 0x00000001 168 #define AM_REG_CACHECTRL_CACHECFG_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001) 169 170 //***************************************************************************** 171 // 172 // CACHECTRL_FLASHCFG - Flash Control Register 173 // 174 //***************************************************************************** 175 // Sets read waitstates for flash accesses (in clock cycles). This should be 176 // left at the default value for normal flash operation. 177 #define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_S 0 178 #define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT_M 0x00000007 179 #define AM_REG_CACHECTRL_FLASHCFG_RD_WAIT(n) (((uint32_t)(n) << 0) & 0x00000007) 180 181 //***************************************************************************** 182 // 183 // CACHECTRL_CACHECTRL - Cache Control 184 // 185 //***************************************************************************** 186 // Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will 187 // enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash 188 // access occurs. Wake from SLM requires ~5us, so this should only be set if 189 // the flash will not be accessed for reasonably long time. 190 #define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE_S 10 191 #define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE_M 0x00000400 192 #define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE(n) (((uint32_t)(n) << 10) & 0x00000400) 193 194 // Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. 195 // Performing a flash read will also wake the array. 196 #define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE_S 9 197 #define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE_M 0x00000200 198 #define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE(n) (((uint32_t)(n) << 9) & 0x00000200) 199 200 // Flash Sleep Mode Status. When 1, flash instance 1 is asleep. 201 #define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_S 8 202 #define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_M 0x00000100 203 #define AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS(n) (((uint32_t)(n) << 8) & 0x00000100) 204 205 // Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will 206 // enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash 207 // access occurs. Wake from SLM requires ~5us, so this should only be set if 208 // the flash will not be accessed for reasonably long time. 209 #define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE_S 6 210 #define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE_M 0x00000040 211 #define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE(n) (((uint32_t)(n) << 6) & 0x00000040) 212 213 // Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. 214 // Performing a flash read will also wake the array. 215 #define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE_S 5 216 #define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE_M 0x00000020 217 #define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE(n) (((uint32_t)(n) << 5) & 0x00000020) 218 219 // Flash Sleep Mode Status. When 1, flash instance 0 is asleep. 220 #define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_S 4 221 #define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_M 0x00000010 222 #define AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS(n) (((uint32_t)(n) << 4) & 0x00000010) 223 224 // Cache Ready Status. A value of 1 indicates the cache is enabled and not 225 // processing an invalidate operation. 226 #define AM_REG_CACHECTRL_CACHECTRL_CACHE_READY_S 2 227 #define AM_REG_CACHECTRL_CACHECTRL_CACHE_READY_M 0x00000004 228 #define AM_REG_CACHECTRL_CACHECTRL_CACHE_READY(n) (((uint32_t)(n) << 2) & 0x00000004) 229 230 // Writing a 1 to this bitfield will reset the cache monitor statistics 231 // (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling 232 // the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values 233 // until the stats are reset by writing this bitfield. 234 #define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_S 1 235 #define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_M 0x00000002 236 #define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT(n) (((uint32_t)(n) << 1) & 0x00000002) 237 #define AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_CLEAR 0x00000002 238 239 // Writing a 1 to this bitfield invalidates the flash cache contents. 240 #define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_S 0 241 #define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_M 0x00000001 242 #define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE(n) (((uint32_t)(n) << 0) & 0x00000001) 243 #define AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_GO 0x00000001 244 245 //***************************************************************************** 246 // 247 // CACHECTRL_NCR0START - Flash Cache Noncachable Region 0 Start Address. 248 // 249 //***************************************************************************** 250 // Start address for non-cacheable region 0. The physical address of the start 251 // of this region should be programmed to this register and must be aligned to a 252 // 16-byte boundary (thus the lower 4 address bits are unused). 253 #define AM_REG_CACHECTRL_NCR0START_ADDR_S 4 254 #define AM_REG_CACHECTRL_NCR0START_ADDR_M 0x000FFFF0 255 #define AM_REG_CACHECTRL_NCR0START_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0) 256 257 //***************************************************************************** 258 // 259 // CACHECTRL_NCR0END - Flash Cache Noncachable Region 0 End 260 // 261 //***************************************************************************** 262 // End address for non-cacheable region 0. The physical address of the end of 263 // this region should be programmed to this register and must be aligned to a 264 // 16-byte boundary (thus the lower 4 address bits are unused). 265 #define AM_REG_CACHECTRL_NCR0END_ADDR_S 4 266 #define AM_REG_CACHECTRL_NCR0END_ADDR_M 0x000FFFF0 267 #define AM_REG_CACHECTRL_NCR0END_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0) 268 269 //***************************************************************************** 270 // 271 // CACHECTRL_NCR1START - Flash Cache Noncachable Region 1 Start 272 // 273 //***************************************************************************** 274 // Start address for non-cacheable region 1. The physical address of the start 275 // of this region should be programmed to this register and must be aligned to a 276 // 16-byte boundary (thus the lower 4 address bits are unused). 277 #define AM_REG_CACHECTRL_NCR1START_ADDR_S 4 278 #define AM_REG_CACHECTRL_NCR1START_ADDR_M 0x000FFFF0 279 #define AM_REG_CACHECTRL_NCR1START_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0) 280 281 //***************************************************************************** 282 // 283 // CACHECTRL_NCR1END - Flash Cache Noncachable Region 1 End 284 // 285 //***************************************************************************** 286 // End address for non-cacheable region 1. The physical address of the end of 287 // this region should be programmed to this register and must be aligned to a 288 // 16-byte boundary (thus the lower 4 address bits are unused). 289 #define AM_REG_CACHECTRL_NCR1END_ADDR_S 4 290 #define AM_REG_CACHECTRL_NCR1END_ADDR_M 0x000FFFF0 291 #define AM_REG_CACHECTRL_NCR1END_ADDR(n) (((uint32_t)(n) << 4) & 0x000FFFF0) 292 293 //***************************************************************************** 294 // 295 // CACHECTRL_CACHEMODE - Flash Cache Mode Register. Used to trim 296 // performance/power. 297 // 298 //***************************************************************************** 299 // Disallow Simultaneous Data RAM reads (from 2 line hits on each bus). Value 300 // should be left at zero for optimal performance. 301 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_S 5 302 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6_M 0x00000020 303 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE6(n) (((uint32_t)(n) << 5) & 0x00000020) 304 305 // Disallow Data RAM reads (from line hits) during lookup read ops. Value 306 // should be left at zero for optimal performance. 307 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_S 4 308 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5_M 0x00000010 309 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE5(n) (((uint32_t)(n) << 4) & 0x00000010) 310 311 // Disallow Data RAM reads (from line hits) on tag RAM fill cycles. Value should 312 // be left at zero for optimal performance. 313 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_S 3 314 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4_M 0x00000008 315 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE4(n) (((uint32_t)(n) << 3) & 0x00000008) 316 317 // Disallow cache data RAM writes on data RAM read cycles. Value should be left 318 // at zero for optimal performance. 319 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_S 2 320 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3_M 0x00000004 321 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE3(n) (((uint32_t)(n) << 2) & 0x00000004) 322 323 // Disallow cache data RAM writes on tag RAM read cycles. Value should be left 324 // at zero for optimal performance. 325 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_S 1 326 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2_M 0x00000002 327 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE2(n) (((uint32_t)(n) << 1) & 0x00000002) 328 329 // Disallow cache data RAM writes on tag RAM fill cycles. Value should be left 330 // at zero for optimal performance. 331 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_S 0 332 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1_M 0x00000001 333 #define AM_REG_CACHECTRL_CACHEMODE_THROTTLE1(n) (((uint32_t)(n) << 0) & 0x00000001) 334 335 //***************************************************************************** 336 // 337 // CACHECTRL_DMON0 - Data Cache Total Accesses 338 // 339 //***************************************************************************** 340 // Total accesses to data cache 341 #define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_S 0 342 #define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT_M 0xFFFFFFFF 343 #define AM_REG_CACHECTRL_DMON0_DACCESS_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 344 345 //***************************************************************************** 346 // 347 // CACHECTRL_DMON1 - Data Cache Tag Lookups 348 // 349 //***************************************************************************** 350 // Total tag lookups from data cache 351 #define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_S 0 352 #define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT_M 0xFFFFFFFF 353 #define AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 354 355 //***************************************************************************** 356 // 357 // CACHECTRL_DMON2 - Data Cache Hits 358 // 359 //***************************************************************************** 360 // Cache hits from lookup operations 361 #define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_S 0 362 #define AM_REG_CACHECTRL_DMON2_DHIT_COUNT_M 0xFFFFFFFF 363 #define AM_REG_CACHECTRL_DMON2_DHIT_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 364 365 //***************************************************************************** 366 // 367 // CACHECTRL_DMON3 - Data Cache Line Hits 368 // 369 //***************************************************************************** 370 // Cache hits from line cache 371 #define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_S 0 372 #define AM_REG_CACHECTRL_DMON3_DLINE_COUNT_M 0xFFFFFFFF 373 #define AM_REG_CACHECTRL_DMON3_DLINE_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 374 375 //***************************************************************************** 376 // 377 // CACHECTRL_IMON0 - Instruction Cache Total Accesses 378 // 379 //***************************************************************************** 380 // Total accesses to Instruction cache 381 #define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_S 0 382 #define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT_M 0xFFFFFFFF 383 #define AM_REG_CACHECTRL_IMON0_IACCESS_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 384 385 //***************************************************************************** 386 // 387 // CACHECTRL_IMON1 - Instruction Cache Tag Lookups 388 // 389 //***************************************************************************** 390 // Total tag lookups from Instruction cache 391 #define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_S 0 392 #define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT_M 0xFFFFFFFF 393 #define AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 394 395 //***************************************************************************** 396 // 397 // CACHECTRL_IMON2 - Instruction Cache Hits 398 // 399 //***************************************************************************** 400 // Cache hits from lookup operations 401 #define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_S 0 402 #define AM_REG_CACHECTRL_IMON2_IHIT_COUNT_M 0xFFFFFFFF 403 #define AM_REG_CACHECTRL_IMON2_IHIT_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 404 405 //***************************************************************************** 406 // 407 // CACHECTRL_IMON3 - Instruction Cache Line Hits 408 // 409 //***************************************************************************** 410 // Cache hits from line cache 411 #define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_S 0 412 #define AM_REG_CACHECTRL_IMON3_ILINE_COUNT_M 0xFFFFFFFF 413 #define AM_REG_CACHECTRL_IMON3_ILINE_COUNT(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 414 415 #endif // AM_REG_CACHECTRL_H 416