1 //***************************************************************************** 2 // 3 // am_reg_iomstr.h 4 //! @file 5 //! 6 //! @brief Register macros for the IOMSTR module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_IOMSTR_H 45 #define AM_REG_IOMSTR_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (6 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_IOMSTR_NUM_MODULES 6 53 #define AM_REG_IOMSTRn(n) \ 54 (REG_IOMSTR_BASEADDR + 0x00001000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_IOMSTR_FIFO_O 0x00000000 62 #define AM_REG_IOMSTR_FIFOPTR_O 0x00000100 63 #define AM_REG_IOMSTR_TLNGTH_O 0x00000104 64 #define AM_REG_IOMSTR_FIFOTHR_O 0x00000108 65 #define AM_REG_IOMSTR_CLKCFG_O 0x0000010C 66 #define AM_REG_IOMSTR_CMD_O 0x00000110 67 #define AM_REG_IOMSTR_CMDRPT_O 0x00000114 68 #define AM_REG_IOMSTR_STATUS_O 0x00000118 69 #define AM_REG_IOMSTR_CFG_O 0x0000011C 70 #define AM_REG_IOMSTR_INTEN_O 0x00000200 71 #define AM_REG_IOMSTR_INTSTAT_O 0x00000204 72 #define AM_REG_IOMSTR_INTCLR_O 0x00000208 73 #define AM_REG_IOMSTR_INTSET_O 0x0000020C 74 75 //***************************************************************************** 76 // 77 // IOMSTR_INTEN - IO Master Interrupts: Enable 78 // 79 //***************************************************************************** 80 // This is the arbitration loss interrupt. This error occurs if another master 81 // collides with an IO Master transfer. Generally, the IOM started an operation 82 // but found SDA already low. 83 #define AM_REG_IOMSTR_INTEN_ARB_S 10 84 #define AM_REG_IOMSTR_INTEN_ARB_M 0x00000400 85 #define AM_REG_IOMSTR_INTEN_ARB(n) (((uint32_t)(n) << 10) & 0x00000400) 86 87 // This is the STOP command interrupt. A STOP bit was detected by the IOM. 88 #define AM_REG_IOMSTR_INTEN_STOP_S 9 89 #define AM_REG_IOMSTR_INTEN_STOP_M 0x00000200 90 #define AM_REG_IOMSTR_INTEN_STOP(n) (((uint32_t)(n) << 9) & 0x00000200) 91 92 // This is the START command interrupt. A START from another master was 93 // detected. Software must wait for a STOP before proceeding. 94 #define AM_REG_IOMSTR_INTEN_START_S 8 95 #define AM_REG_IOMSTR_INTEN_START_M 0x00000100 96 #define AM_REG_IOMSTR_INTEN_START(n) (((uint32_t)(n) << 8) & 0x00000100) 97 98 // This is the illegal command interrupt. Software attempted to issue a CMD 99 // while another CMD was already in progress. Or an attempt was made to issue a 100 // non-zero-length write CMD with an empty FIFO. 101 #define AM_REG_IOMSTR_INTEN_ICMD_S 7 102 #define AM_REG_IOMSTR_INTEN_ICMD_M 0x00000080 103 #define AM_REG_IOMSTR_INTEN_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080) 104 105 // This is the illegal FIFO access interrupt. An attempt was made to read the 106 // FIFO during a write CMD. Or an attempt was made to write the FIFO on a read 107 // CMD. 108 #define AM_REG_IOMSTR_INTEN_IACC_S 6 109 #define AM_REG_IOMSTR_INTEN_IACC_M 0x00000040 110 #define AM_REG_IOMSTR_INTEN_IACC(n) (((uint32_t)(n) << 6) & 0x00000040) 111 112 // This is the WTLEN interrupt. 113 #define AM_REG_IOMSTR_INTEN_WTLEN_S 5 114 #define AM_REG_IOMSTR_INTEN_WTLEN_M 0x00000020 115 #define AM_REG_IOMSTR_INTEN_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020) 116 117 // This is the I2C NAK interrupt. The expected ACK from the slave was not 118 // received by the IOM. 119 #define AM_REG_IOMSTR_INTEN_NAK_S 4 120 #define AM_REG_IOMSTR_INTEN_NAK_M 0x00000010 121 #define AM_REG_IOMSTR_INTEN_NAK(n) (((uint32_t)(n) << 4) & 0x00000010) 122 123 // This is the Write FIFO Overflow interrupt. An attempt was made to write the 124 // FIFO while it was full (i.e. while FIFOSIZ > 124). 125 #define AM_REG_IOMSTR_INTEN_FOVFL_S 3 126 #define AM_REG_IOMSTR_INTEN_FOVFL_M 0x00000008 127 #define AM_REG_IOMSTR_INTEN_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008) 128 129 // This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO 130 // when empty (i.e. while FIFOSIZ less than 4). 131 #define AM_REG_IOMSTR_INTEN_FUNDFL_S 2 132 #define AM_REG_IOMSTR_INTEN_FUNDFL_M 0x00000004 133 #define AM_REG_IOMSTR_INTEN_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 134 135 // This is the FIFO Threshold interrupt. 136 #define AM_REG_IOMSTR_INTEN_THR_S 1 137 #define AM_REG_IOMSTR_INTEN_THR_M 0x00000002 138 #define AM_REG_IOMSTR_INTEN_THR(n) (((uint32_t)(n) << 1) & 0x00000002) 139 140 // This is the Command Complete interrupt. 141 #define AM_REG_IOMSTR_INTEN_CMDCMP_S 0 142 #define AM_REG_IOMSTR_INTEN_CMDCMP_M 0x00000001 143 #define AM_REG_IOMSTR_INTEN_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001) 144 145 //***************************************************************************** 146 // 147 // IOMSTR_INTSTAT - IO Master Interrupts: Status 148 // 149 //***************************************************************************** 150 // This is the arbitration loss interrupt. This error occurs if another master 151 // collides with an IO Master transfer. Generally, the IOM started an operation 152 // but found SDA already low. 153 #define AM_REG_IOMSTR_INTSTAT_ARB_S 10 154 #define AM_REG_IOMSTR_INTSTAT_ARB_M 0x00000400 155 #define AM_REG_IOMSTR_INTSTAT_ARB(n) (((uint32_t)(n) << 10) & 0x00000400) 156 157 // This is the STOP command interrupt. A STOP bit was detected by the IOM. 158 #define AM_REG_IOMSTR_INTSTAT_STOP_S 9 159 #define AM_REG_IOMSTR_INTSTAT_STOP_M 0x00000200 160 #define AM_REG_IOMSTR_INTSTAT_STOP(n) (((uint32_t)(n) << 9) & 0x00000200) 161 162 // This is the START command interrupt. A START from another master was 163 // detected. Software must wait for a STOP before proceeding. 164 #define AM_REG_IOMSTR_INTSTAT_START_S 8 165 #define AM_REG_IOMSTR_INTSTAT_START_M 0x00000100 166 #define AM_REG_IOMSTR_INTSTAT_START(n) (((uint32_t)(n) << 8) & 0x00000100) 167 168 // This is the illegal command interrupt. Software attempted to issue a CMD 169 // while another CMD was already in progress. Or an attempt was made to issue a 170 // non-zero-length write CMD with an empty FIFO. 171 #define AM_REG_IOMSTR_INTSTAT_ICMD_S 7 172 #define AM_REG_IOMSTR_INTSTAT_ICMD_M 0x00000080 173 #define AM_REG_IOMSTR_INTSTAT_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080) 174 175 // This is the illegal FIFO access interrupt. An attempt was made to read the 176 // FIFO during a write CMD. Or an attempt was made to write the FIFO on a read 177 // CMD. 178 #define AM_REG_IOMSTR_INTSTAT_IACC_S 6 179 #define AM_REG_IOMSTR_INTSTAT_IACC_M 0x00000040 180 #define AM_REG_IOMSTR_INTSTAT_IACC(n) (((uint32_t)(n) << 6) & 0x00000040) 181 182 // This is the WTLEN interrupt. 183 #define AM_REG_IOMSTR_INTSTAT_WTLEN_S 5 184 #define AM_REG_IOMSTR_INTSTAT_WTLEN_M 0x00000020 185 #define AM_REG_IOMSTR_INTSTAT_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020) 186 187 // This is the I2C NAK interrupt. The expected ACK from the slave was not 188 // received by the IOM. 189 #define AM_REG_IOMSTR_INTSTAT_NAK_S 4 190 #define AM_REG_IOMSTR_INTSTAT_NAK_M 0x00000010 191 #define AM_REG_IOMSTR_INTSTAT_NAK(n) (((uint32_t)(n) << 4) & 0x00000010) 192 193 // This is the Write FIFO Overflow interrupt. An attempt was made to write the 194 // FIFO while it was full (i.e. while FIFOSIZ > 124). 195 #define AM_REG_IOMSTR_INTSTAT_FOVFL_S 3 196 #define AM_REG_IOMSTR_INTSTAT_FOVFL_M 0x00000008 197 #define AM_REG_IOMSTR_INTSTAT_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008) 198 199 // This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO 200 // when empty (i.e. while FIFOSIZ less than 4). 201 #define AM_REG_IOMSTR_INTSTAT_FUNDFL_S 2 202 #define AM_REG_IOMSTR_INTSTAT_FUNDFL_M 0x00000004 203 #define AM_REG_IOMSTR_INTSTAT_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 204 205 // This is the FIFO Threshold interrupt. 206 #define AM_REG_IOMSTR_INTSTAT_THR_S 1 207 #define AM_REG_IOMSTR_INTSTAT_THR_M 0x00000002 208 #define AM_REG_IOMSTR_INTSTAT_THR(n) (((uint32_t)(n) << 1) & 0x00000002) 209 210 // This is the Command Complete interrupt. 211 #define AM_REG_IOMSTR_INTSTAT_CMDCMP_S 0 212 #define AM_REG_IOMSTR_INTSTAT_CMDCMP_M 0x00000001 213 #define AM_REG_IOMSTR_INTSTAT_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001) 214 215 //***************************************************************************** 216 // 217 // IOMSTR_INTCLR - IO Master Interrupts: Clear 218 // 219 //***************************************************************************** 220 // This is the arbitration loss interrupt. This error occurs if another master 221 // collides with an IO Master transfer. Generally, the IOM started an operation 222 // but found SDA already low. 223 #define AM_REG_IOMSTR_INTCLR_ARB_S 10 224 #define AM_REG_IOMSTR_INTCLR_ARB_M 0x00000400 225 #define AM_REG_IOMSTR_INTCLR_ARB(n) (((uint32_t)(n) << 10) & 0x00000400) 226 227 // This is the STOP command interrupt. A STOP bit was detected by the IOM. 228 #define AM_REG_IOMSTR_INTCLR_STOP_S 9 229 #define AM_REG_IOMSTR_INTCLR_STOP_M 0x00000200 230 #define AM_REG_IOMSTR_INTCLR_STOP(n) (((uint32_t)(n) << 9) & 0x00000200) 231 232 // This is the START command interrupt. A START from another master was 233 // detected. Software must wait for a STOP before proceeding. 234 #define AM_REG_IOMSTR_INTCLR_START_S 8 235 #define AM_REG_IOMSTR_INTCLR_START_M 0x00000100 236 #define AM_REG_IOMSTR_INTCLR_START(n) (((uint32_t)(n) << 8) & 0x00000100) 237 238 // This is the illegal command interrupt. Software attempted to issue a CMD 239 // while another CMD was already in progress. Or an attempt was made to issue a 240 // non-zero-length write CMD with an empty FIFO. 241 #define AM_REG_IOMSTR_INTCLR_ICMD_S 7 242 #define AM_REG_IOMSTR_INTCLR_ICMD_M 0x00000080 243 #define AM_REG_IOMSTR_INTCLR_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080) 244 245 // This is the illegal FIFO access interrupt. An attempt was made to read the 246 // FIFO during a write CMD. Or an attempt was made to write the FIFO on a read 247 // CMD. 248 #define AM_REG_IOMSTR_INTCLR_IACC_S 6 249 #define AM_REG_IOMSTR_INTCLR_IACC_M 0x00000040 250 #define AM_REG_IOMSTR_INTCLR_IACC(n) (((uint32_t)(n) << 6) & 0x00000040) 251 252 // This is the WTLEN interrupt. 253 #define AM_REG_IOMSTR_INTCLR_WTLEN_S 5 254 #define AM_REG_IOMSTR_INTCLR_WTLEN_M 0x00000020 255 #define AM_REG_IOMSTR_INTCLR_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020) 256 257 // This is the I2C NAK interrupt. The expected ACK from the slave was not 258 // received by the IOM. 259 #define AM_REG_IOMSTR_INTCLR_NAK_S 4 260 #define AM_REG_IOMSTR_INTCLR_NAK_M 0x00000010 261 #define AM_REG_IOMSTR_INTCLR_NAK(n) (((uint32_t)(n) << 4) & 0x00000010) 262 263 // This is the Write FIFO Overflow interrupt. An attempt was made to write the 264 // FIFO while it was full (i.e. while FIFOSIZ > 124). 265 #define AM_REG_IOMSTR_INTCLR_FOVFL_S 3 266 #define AM_REG_IOMSTR_INTCLR_FOVFL_M 0x00000008 267 #define AM_REG_IOMSTR_INTCLR_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008) 268 269 // This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO 270 // when empty (i.e. while FIFOSIZ less than 4). 271 #define AM_REG_IOMSTR_INTCLR_FUNDFL_S 2 272 #define AM_REG_IOMSTR_INTCLR_FUNDFL_M 0x00000004 273 #define AM_REG_IOMSTR_INTCLR_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 274 275 // This is the FIFO Threshold interrupt. 276 #define AM_REG_IOMSTR_INTCLR_THR_S 1 277 #define AM_REG_IOMSTR_INTCLR_THR_M 0x00000002 278 #define AM_REG_IOMSTR_INTCLR_THR(n) (((uint32_t)(n) << 1) & 0x00000002) 279 280 // This is the Command Complete interrupt. 281 #define AM_REG_IOMSTR_INTCLR_CMDCMP_S 0 282 #define AM_REG_IOMSTR_INTCLR_CMDCMP_M 0x00000001 283 #define AM_REG_IOMSTR_INTCLR_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001) 284 285 //***************************************************************************** 286 // 287 // IOMSTR_INTSET - IO Master Interrupts: Set 288 // 289 //***************************************************************************** 290 // This is the arbitration loss interrupt. This error occurs if another master 291 // collides with an IO Master transfer. Generally, the IOM started an operation 292 // but found SDA already low. 293 #define AM_REG_IOMSTR_INTSET_ARB_S 10 294 #define AM_REG_IOMSTR_INTSET_ARB_M 0x00000400 295 #define AM_REG_IOMSTR_INTSET_ARB(n) (((uint32_t)(n) << 10) & 0x00000400) 296 297 // This is the STOP command interrupt. A STOP bit was detected by the IOM. 298 #define AM_REG_IOMSTR_INTSET_STOP_S 9 299 #define AM_REG_IOMSTR_INTSET_STOP_M 0x00000200 300 #define AM_REG_IOMSTR_INTSET_STOP(n) (((uint32_t)(n) << 9) & 0x00000200) 301 302 // This is the START command interrupt. A START from another master was 303 // detected. Software must wait for a STOP before proceeding. 304 #define AM_REG_IOMSTR_INTSET_START_S 8 305 #define AM_REG_IOMSTR_INTSET_START_M 0x00000100 306 #define AM_REG_IOMSTR_INTSET_START(n) (((uint32_t)(n) << 8) & 0x00000100) 307 308 // This is the illegal command interrupt. Software attempted to issue a CMD 309 // while another CMD was already in progress. Or an attempt was made to issue a 310 // non-zero-length write CMD with an empty FIFO. 311 #define AM_REG_IOMSTR_INTSET_ICMD_S 7 312 #define AM_REG_IOMSTR_INTSET_ICMD_M 0x00000080 313 #define AM_REG_IOMSTR_INTSET_ICMD(n) (((uint32_t)(n) << 7) & 0x00000080) 314 315 // This is the illegal FIFO access interrupt. An attempt was made to read the 316 // FIFO during a write CMD. Or an attempt was made to write the FIFO on a read 317 // CMD. 318 #define AM_REG_IOMSTR_INTSET_IACC_S 6 319 #define AM_REG_IOMSTR_INTSET_IACC_M 0x00000040 320 #define AM_REG_IOMSTR_INTSET_IACC(n) (((uint32_t)(n) << 6) & 0x00000040) 321 322 // This is the WTLEN interrupt. 323 #define AM_REG_IOMSTR_INTSET_WTLEN_S 5 324 #define AM_REG_IOMSTR_INTSET_WTLEN_M 0x00000020 325 #define AM_REG_IOMSTR_INTSET_WTLEN(n) (((uint32_t)(n) << 5) & 0x00000020) 326 327 // This is the I2C NAK interrupt. The expected ACK from the slave was not 328 // received by the IOM. 329 #define AM_REG_IOMSTR_INTSET_NAK_S 4 330 #define AM_REG_IOMSTR_INTSET_NAK_M 0x00000010 331 #define AM_REG_IOMSTR_INTSET_NAK(n) (((uint32_t)(n) << 4) & 0x00000010) 332 333 // This is the Write FIFO Overflow interrupt. An attempt was made to write the 334 // FIFO while it was full (i.e. while FIFOSIZ > 124). 335 #define AM_REG_IOMSTR_INTSET_FOVFL_S 3 336 #define AM_REG_IOMSTR_INTSET_FOVFL_M 0x00000008 337 #define AM_REG_IOMSTR_INTSET_FOVFL(n) (((uint32_t)(n) << 3) & 0x00000008) 338 339 // This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO 340 // when empty (i.e. while FIFOSIZ less than 4). 341 #define AM_REG_IOMSTR_INTSET_FUNDFL_S 2 342 #define AM_REG_IOMSTR_INTSET_FUNDFL_M 0x00000004 343 #define AM_REG_IOMSTR_INTSET_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 344 345 // This is the FIFO Threshold interrupt. 346 #define AM_REG_IOMSTR_INTSET_THR_S 1 347 #define AM_REG_IOMSTR_INTSET_THR_M 0x00000002 348 #define AM_REG_IOMSTR_INTSET_THR(n) (((uint32_t)(n) << 1) & 0x00000002) 349 350 // This is the Command Complete interrupt. 351 #define AM_REG_IOMSTR_INTSET_CMDCMP_S 0 352 #define AM_REG_IOMSTR_INTSET_CMDCMP_M 0x00000001 353 #define AM_REG_IOMSTR_INTSET_CMDCMP(n) (((uint32_t)(n) << 0) & 0x00000001) 354 355 //***************************************************************************** 356 // 357 // IOMSTR_FIFO - FIFO Access Port 358 // 359 //***************************************************************************** 360 // FIFO access port. 361 #define AM_REG_IOMSTR_FIFO_FIFO_S 0 362 #define AM_REG_IOMSTR_FIFO_FIFO_M 0xFFFFFFFF 363 #define AM_REG_IOMSTR_FIFO_FIFO(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 364 365 //***************************************************************************** 366 // 367 // IOMSTR_FIFOPTR - Current FIFO Pointers 368 // 369 //***************************************************************************** 370 // The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 371 // 64-FIFOSIZ if FULLDUP = 1)). 372 #define AM_REG_IOMSTR_FIFOPTR_FIFOREM_S 16 373 #define AM_REG_IOMSTR_FIFOPTR_FIFOREM_M 0x00FF0000 374 #define AM_REG_IOMSTR_FIFOPTR_FIFOREM(n) (((uint32_t)(n) << 16) & 0x00FF0000) 375 376 // The number of bytes currently in the FIFO. 377 #define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ_S 0 378 #define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ_M 0x000000FF 379 #define AM_REG_IOMSTR_FIFOPTR_FIFOSIZ(n) (((uint32_t)(n) << 0) & 0x000000FF) 380 381 //***************************************************************************** 382 // 383 // IOMSTR_TLNGTH - Transfer Length 384 // 385 //***************************************************************************** 386 // Remaining transfer length. 387 #define AM_REG_IOMSTR_TLNGTH_TLNGTH_S 0 388 #define AM_REG_IOMSTR_TLNGTH_TLNGTH_M 0x00000FFF 389 #define AM_REG_IOMSTR_TLNGTH_TLNGTH(n) (((uint32_t)(n) << 0) & 0x00000FFF) 390 391 //***************************************************************************** 392 // 393 // IOMSTR_FIFOTHR - FIFO Threshold Configuration 394 // 395 //***************************************************************************** 396 // FIFO write threshold. 397 #define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR_S 8 398 #define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR_M 0x00007F00 399 #define AM_REG_IOMSTR_FIFOTHR_FIFOWTHR(n) (((uint32_t)(n) << 8) & 0x00007F00) 400 401 // FIFO read threshold. 402 #define AM_REG_IOMSTR_FIFOTHR_FIFORTHR_S 0 403 #define AM_REG_IOMSTR_FIFOTHR_FIFORTHR_M 0x0000007F 404 #define AM_REG_IOMSTR_FIFOTHR_FIFORTHR(n) (((uint32_t)(n) << 0) & 0x0000007F) 405 406 //***************************************************************************** 407 // 408 // IOMSTR_CLKCFG - I/O Clock Configuration 409 // 410 //***************************************************************************** 411 // Clock total count minus 1. 412 #define AM_REG_IOMSTR_CLKCFG_TOTPER_S 24 413 #define AM_REG_IOMSTR_CLKCFG_TOTPER_M 0xFF000000 414 #define AM_REG_IOMSTR_CLKCFG_TOTPER(n) (((uint32_t)(n) << 24) & 0xFF000000) 415 416 // Clock low count minus 1. 417 #define AM_REG_IOMSTR_CLKCFG_LOWPER_S 16 418 #define AM_REG_IOMSTR_CLKCFG_LOWPER_M 0x00FF0000 419 #define AM_REG_IOMSTR_CLKCFG_LOWPER(n) (((uint32_t)(n) << 16) & 0x00FF0000) 420 421 // Enable clock division by TOTPER. 422 #define AM_REG_IOMSTR_CLKCFG_DIVEN_S 12 423 #define AM_REG_IOMSTR_CLKCFG_DIVEN_M 0x00001000 424 #define AM_REG_IOMSTR_CLKCFG_DIVEN(n) (((uint32_t)(n) << 12) & 0x00001000) 425 #define AM_REG_IOMSTR_CLKCFG_DIVEN_DIS 0x00000000 426 #define AM_REG_IOMSTR_CLKCFG_DIVEN_EN 0x00001000 427 428 // Enable divide by 3. 429 #define AM_REG_IOMSTR_CLKCFG_DIV3_S 11 430 #define AM_REG_IOMSTR_CLKCFG_DIV3_M 0x00000800 431 #define AM_REG_IOMSTR_CLKCFG_DIV3(n) (((uint32_t)(n) << 11) & 0x00000800) 432 #define AM_REG_IOMSTR_CLKCFG_DIV3_DIS 0x00000000 433 #define AM_REG_IOMSTR_CLKCFG_DIV3_EN 0x00000800 434 435 // Select the input clock frequency. 436 #define AM_REG_IOMSTR_CLKCFG_FSEL_S 8 437 #define AM_REG_IOMSTR_CLKCFG_FSEL_M 0x00000700 438 #define AM_REG_IOMSTR_CLKCFG_FSEL(n) (((uint32_t)(n) << 8) & 0x00000700) 439 #define AM_REG_IOMSTR_CLKCFG_FSEL_MIN_PWR 0x00000000 440 #define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC 0x00000100 441 #define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV2 0x00000200 442 #define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV4 0x00000300 443 #define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV8 0x00000400 444 #define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV16 0x00000500 445 #define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV32 0x00000600 446 #define AM_REG_IOMSTR_CLKCFG_FSEL_HFRC_DIV64 0x00000700 447 448 //***************************************************************************** 449 // 450 // IOMSTR_CMD - Command Register 451 // 452 //***************************************************************************** 453 // This register holds the I/O Command 454 #define AM_REG_IOMSTR_CMD_CMD_S 0 455 #define AM_REG_IOMSTR_CMD_CMD_M 0xFFFFFFFF 456 #define AM_REG_IOMSTR_CMD_CMD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 457 458 //***************************************************************************** 459 // 460 // IOMSTR_CMDRPT - Command Repeat Register 461 // 462 //***************************************************************************** 463 // These bits hold the Command repeat count. 464 #define AM_REG_IOMSTR_CMDRPT_CMDRPT_S 0 465 #define AM_REG_IOMSTR_CMDRPT_CMDRPT_M 0x0000001F 466 #define AM_REG_IOMSTR_CMDRPT_CMDRPT(n) (((uint32_t)(n) << 0) & 0x0000001F) 467 468 //***************************************************************************** 469 // 470 // IOMSTR_STATUS - Status Register 471 // 472 //***************************************************************************** 473 // This bit indicates if the I/O state machine is IDLE. 474 #define AM_REG_IOMSTR_STATUS_IDLEST_S 2 475 #define AM_REG_IOMSTR_STATUS_IDLEST_M 0x00000004 476 #define AM_REG_IOMSTR_STATUS_IDLEST(n) (((uint32_t)(n) << 2) & 0x00000004) 477 #define AM_REG_IOMSTR_STATUS_IDLEST_IDLE 0x00000004 478 479 // This bit indicates if the I/O Command is active. 480 #define AM_REG_IOMSTR_STATUS_CMDACT_S 1 481 #define AM_REG_IOMSTR_STATUS_CMDACT_M 0x00000002 482 #define AM_REG_IOMSTR_STATUS_CMDACT(n) (((uint32_t)(n) << 1) & 0x00000002) 483 #define AM_REG_IOMSTR_STATUS_CMDACT_ACTIVE 0x00000002 484 485 // This bit indicates if an error interrupt has occurred. 486 #define AM_REG_IOMSTR_STATUS_ERR_S 0 487 #define AM_REG_IOMSTR_STATUS_ERR_M 0x00000001 488 #define AM_REG_IOMSTR_STATUS_ERR(n) (((uint32_t)(n) << 0) & 0x00000001) 489 #define AM_REG_IOMSTR_STATUS_ERR_ERROR 0x00000001 490 491 //***************************************************************************** 492 // 493 // IOMSTR_CFG - I/O Master Configuration 494 // 495 //***************************************************************************** 496 // This bit enables the IO Master. 497 #define AM_REG_IOMSTR_CFG_IFCEN_S 31 498 #define AM_REG_IOMSTR_CFG_IFCEN_M 0x80000000 499 #define AM_REG_IOMSTR_CFG_IFCEN(n) (((uint32_t)(n) << 31) & 0x80000000) 500 #define AM_REG_IOMSTR_CFG_IFCEN_DIS 0x00000000 501 #define AM_REG_IOMSTR_CFG_IFCEN_EN 0x80000000 502 503 // This bit selects the read flow control signal polarity. 504 #define AM_REG_IOMSTR_CFG_RDFCPOL_S 14 505 #define AM_REG_IOMSTR_CFG_RDFCPOL_M 0x00004000 506 #define AM_REG_IOMSTR_CFG_RDFCPOL(n) (((uint32_t)(n) << 14) & 0x00004000) 507 #define AM_REG_IOMSTR_CFG_RDFCPOL_HIGH 0x00000000 508 #define AM_REG_IOMSTR_CFG_RDFCPOL_LOW 0x00004000 509 510 // This bit selects the write flow control signal polarity. 511 #define AM_REG_IOMSTR_CFG_WTFCPOL_S 13 512 #define AM_REG_IOMSTR_CFG_WTFCPOL_M 0x00002000 513 #define AM_REG_IOMSTR_CFG_WTFCPOL(n) (((uint32_t)(n) << 13) & 0x00002000) 514 #define AM_REG_IOMSTR_CFG_WTFCPOL_HIGH 0x00000000 515 #define AM_REG_IOMSTR_CFG_WTFCPOL_LOW 0x00002000 516 517 // This bit selects the write mode flow control signal. 518 #define AM_REG_IOMSTR_CFG_WTFCIRQ_S 12 519 #define AM_REG_IOMSTR_CFG_WTFCIRQ_M 0x00001000 520 #define AM_REG_IOMSTR_CFG_WTFCIRQ(n) (((uint32_t)(n) << 12) & 0x00001000) 521 #define AM_REG_IOMSTR_CFG_WTFCIRQ_MISO 0x00000000 522 #define AM_REG_IOMSTR_CFG_WTFCIRQ_IRQ 0x00001000 523 524 // This bit must be left at the default value of 0. 525 #define AM_REG_IOMSTR_CFG_FCDEL_S 11 526 #define AM_REG_IOMSTR_CFG_FCDEL_M 0x00000800 527 #define AM_REG_IOMSTR_CFG_FCDEL(n) (((uint32_t)(n) << 11) & 0x00000800) 528 529 // This bit invewrts MOSI when flow control is enabled. 530 #define AM_REG_IOMSTR_CFG_MOSIINV_S 10 531 #define AM_REG_IOMSTR_CFG_MOSIINV_M 0x00000400 532 #define AM_REG_IOMSTR_CFG_MOSIINV(n) (((uint32_t)(n) << 10) & 0x00000400) 533 #define AM_REG_IOMSTR_CFG_MOSIINV_NORMAL 0x00000000 534 #define AM_REG_IOMSTR_CFG_MOSIINV_INVERT 0x00000400 535 536 // This bit enables read mode flow control. 537 #define AM_REG_IOMSTR_CFG_RDFC_S 9 538 #define AM_REG_IOMSTR_CFG_RDFC_M 0x00000200 539 #define AM_REG_IOMSTR_CFG_RDFC(n) (((uint32_t)(n) << 9) & 0x00000200) 540 #define AM_REG_IOMSTR_CFG_RDFC_DIS 0x00000000 541 #define AM_REG_IOMSTR_CFG_RDFC_EN 0x00000200 542 543 // This bit enables write mode flow control. 544 #define AM_REG_IOMSTR_CFG_WTFC_S 8 545 #define AM_REG_IOMSTR_CFG_WTFC_M 0x00000100 546 #define AM_REG_IOMSTR_CFG_WTFC(n) (((uint32_t)(n) << 8) & 0x00000100) 547 #define AM_REG_IOMSTR_CFG_WTFC_DIS 0x00000000 548 #define AM_REG_IOMSTR_CFG_WTFC_EN 0x00000100 549 550 // This bit selects the preread timing. 551 #define AM_REG_IOMSTR_CFG_STARTRD_S 4 552 #define AM_REG_IOMSTR_CFG_STARTRD_M 0x00000030 553 #define AM_REG_IOMSTR_CFG_STARTRD(n) (((uint32_t)(n) << 4) & 0x00000030) 554 #define AM_REG_IOMSTR_CFG_STARTRD_PRERD0 0x00000000 555 #define AM_REG_IOMSTR_CFG_STARTRD_PRERD1 0x00000010 556 #define AM_REG_IOMSTR_CFG_STARTRD_PRERD2 0x00000020 557 #define AM_REG_IOMSTR_CFG_STARTRD_PRERD3 0x00000030 558 559 // This bit selects full duplex mode. 560 #define AM_REG_IOMSTR_CFG_FULLDUP_S 3 561 #define AM_REG_IOMSTR_CFG_FULLDUP_M 0x00000008 562 #define AM_REG_IOMSTR_CFG_FULLDUP(n) (((uint32_t)(n) << 3) & 0x00000008) 563 #define AM_REG_IOMSTR_CFG_FULLDUP_NORMAL 0x00000000 564 #define AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP 0x00000008 565 566 // This bit selects SPI phase. 567 #define AM_REG_IOMSTR_CFG_SPHA_S 2 568 #define AM_REG_IOMSTR_CFG_SPHA_M 0x00000004 569 #define AM_REG_IOMSTR_CFG_SPHA(n) (((uint32_t)(n) << 2) & 0x00000004) 570 #define AM_REG_IOMSTR_CFG_SPHA_SAMPLE_LEADING_EDGE 0x00000000 571 #define AM_REG_IOMSTR_CFG_SPHA_SAMPLE_TRAILING_EDGE 0x00000004 572 573 // This bit selects SPI polarity. 574 #define AM_REG_IOMSTR_CFG_SPOL_S 1 575 #define AM_REG_IOMSTR_CFG_SPOL_M 0x00000002 576 #define AM_REG_IOMSTR_CFG_SPOL(n) (((uint32_t)(n) << 1) & 0x00000002) 577 #define AM_REG_IOMSTR_CFG_SPOL_CLK_BASE_0 0x00000000 578 #define AM_REG_IOMSTR_CFG_SPOL_CLK_BASE_1 0x00000002 579 580 // This bit selects the I/O interface. 581 #define AM_REG_IOMSTR_CFG_IFCSEL_S 0 582 #define AM_REG_IOMSTR_CFG_IFCSEL_M 0x00000001 583 #define AM_REG_IOMSTR_CFG_IFCSEL(n) (((uint32_t)(n) << 0) & 0x00000001) 584 #define AM_REG_IOMSTR_CFG_IFCSEL_I2C 0x00000000 585 #define AM_REG_IOMSTR_CFG_IFCSEL_SPI 0x00000001 586 587 #endif // AM_REG_IOMSTR_H 588