1 //***************************************************************************** 2 // 3 // am_reg_jedec.h 4 //! @file 5 //! 6 //! @brief Register macros for the JEDEC module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_JEDEC_H 45 #define AM_REG_JEDEC_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_JEDEC_NUM_MODULES 1 53 #define AM_REG_JEDECn(n) \ 54 (REG_JEDEC_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_JEDEC_PID4_O 0xF0000FD0 62 #define AM_REG_JEDEC_PID5_O 0xF0000FD4 63 #define AM_REG_JEDEC_PID6_O 0xF0000FD8 64 #define AM_REG_JEDEC_PID7_O 0xF0000FDC 65 #define AM_REG_JEDEC_PID0_O 0xF0000FE0 66 #define AM_REG_JEDEC_PID1_O 0xF0000FE4 67 #define AM_REG_JEDEC_PID2_O 0xF0000FE8 68 #define AM_REG_JEDEC_PID3_O 0xF0000FEC 69 #define AM_REG_JEDEC_CID0_O 0xF0000FF0 70 #define AM_REG_JEDEC_CID1_O 0xF0000FF4 71 #define AM_REG_JEDEC_CID2_O 0xF0000FF8 72 #define AM_REG_JEDEC_CID3_O 0xF0000FFC 73 74 //***************************************************************************** 75 // 76 // JEDEC_PID4 - JEP Continuation Register 77 // 78 //***************************************************************************** 79 // Contains the JEP Continuation bits. 80 #define AM_REG_JEDEC_PID4_JEPCONT_S 0 81 #define AM_REG_JEDEC_PID4_JEPCONT_M 0x0000000F 82 #define AM_REG_JEDEC_PID4_JEPCONT(n) (((uint32_t)(n) << 0) & 0x0000000F) 83 84 //***************************************************************************** 85 // 86 // JEDEC_PID5 - JEP reserved Register 87 // 88 //***************************************************************************** 89 // Contains the value of 0x00000000. 90 #define AM_REG_JEDEC_PID5_VALUE_S 0 91 #define AM_REG_JEDEC_PID5_VALUE_M 0xFFFFFFFF 92 #define AM_REG_JEDEC_PID5_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 93 94 //***************************************************************************** 95 // 96 // JEDEC_PID6 - JEP reserved Register 97 // 98 //***************************************************************************** 99 // Contains the value of 0x00000000. 100 #define AM_REG_JEDEC_PID6_VALUE_S 0 101 #define AM_REG_JEDEC_PID6_VALUE_M 0xFFFFFFFF 102 #define AM_REG_JEDEC_PID6_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 103 104 //***************************************************************************** 105 // 106 // JEDEC_PID7 - JEP reserved Register 107 // 108 //***************************************************************************** 109 // Contains the value of 0x00000000. 110 #define AM_REG_JEDEC_PID7_VALUE_S 0 111 #define AM_REG_JEDEC_PID7_VALUE_M 0xFFFFFFFF 112 #define AM_REG_JEDEC_PID7_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 113 114 //***************************************************************************** 115 // 116 // JEDEC_PID0 - Ambiq Partnum low byte 117 // 118 //***************************************************************************** 119 // Contains the low 8 bits of the Ambiq Micro device part number. 120 #define AM_REG_JEDEC_PID0_PNL8_S 0 121 #define AM_REG_JEDEC_PID0_PNL8_M 0x000000FF 122 #define AM_REG_JEDEC_PID0_PNL8(n) (((uint32_t)(n) << 0) & 0x000000FF) 123 124 //***************************************************************************** 125 // 126 // JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble. 127 // 128 //***************************************************************************** 129 // Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID 130 // is therefore 0x9B. 131 #define AM_REG_JEDEC_PID1_JEPIDL_S 4 132 #define AM_REG_JEDEC_PID1_JEPIDL_M 0x000000F0 133 #define AM_REG_JEDEC_PID1_JEPIDL(n) (((uint32_t)(n) << 4) & 0x000000F0) 134 135 // Contains the high 4 bits of the Ambiq Micro device part number. 136 #define AM_REG_JEDEC_PID1_PNH4_S 0 137 #define AM_REG_JEDEC_PID1_PNH4_M 0x0000000F 138 #define AM_REG_JEDEC_PID1_PNH4(n) (((uint32_t)(n) << 0) & 0x0000000F) 139 140 //***************************************************************************** 141 // 142 // JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble 143 // 144 //***************************************************************************** 145 // Contains the high 4 bits of the Ambiq Micro CHIPREV (see also 146 // MCUCTRL.CHIPREV). Note that this field will change with each revision of the 147 // chip. 148 #define AM_REG_JEDEC_PID2_CHIPREVH4_S 4 149 #define AM_REG_JEDEC_PID2_CHIPREVH4_M 0x000000F0 150 #define AM_REG_JEDEC_PID2_CHIPREVH4(n) (((uint32_t)(n) << 4) & 0x000000F0) 151 152 // Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this 153 // field is hard-coded to 1. The full JEPID is therefore 0x9B. 154 #define AM_REG_JEDEC_PID2_JEPIDH_S 0 155 #define AM_REG_JEDEC_PID2_JEPIDH_M 0x0000000F 156 #define AM_REG_JEDEC_PID2_JEPIDH(n) (((uint32_t)(n) << 0) & 0x0000000F) 157 158 //***************************************************************************** 159 // 160 // JEDEC_PID3 - Ambiq chip revision high-nibble. 161 // 162 //***************************************************************************** 163 // Contains the low 4 bits of the Ambiq Micro CHIPREV (see also 164 // MCUCTRL.CHIPREV). Note that this field will change with each revision of the 165 // chip. 166 #define AM_REG_JEDEC_PID3_CHIPREVL4_S 4 167 #define AM_REG_JEDEC_PID3_CHIPREVL4_M 0x000000F0 168 #define AM_REG_JEDEC_PID3_CHIPREVL4(n) (((uint32_t)(n) << 4) & 0x000000F0) 169 170 // This field is hard-coded to 0x0. 171 #define AM_REG_JEDEC_PID3_ZERO_S 0 172 #define AM_REG_JEDEC_PID3_ZERO_M 0x0000000F 173 #define AM_REG_JEDEC_PID3_ZERO(n) (((uint32_t)(n) << 0) & 0x0000000F) 174 175 //***************************************************************************** 176 // 177 // JEDEC_CID0 - Coresight ROM Table. 178 // 179 //***************************************************************************** 180 // Coresight ROM Table, CID0. 181 #define AM_REG_JEDEC_CID0_CID_S 0 182 #define AM_REG_JEDEC_CID0_CID_M 0x000000FF 183 #define AM_REG_JEDEC_CID0_CID(n) (((uint32_t)(n) << 0) & 0x000000FF) 184 185 //***************************************************************************** 186 // 187 // JEDEC_CID1 - Coresight ROM Table. 188 // 189 //***************************************************************************** 190 // Coresight ROM Table, CID1. 191 #define AM_REG_JEDEC_CID1_CID_S 0 192 #define AM_REG_JEDEC_CID1_CID_M 0x000000FF 193 #define AM_REG_JEDEC_CID1_CID(n) (((uint32_t)(n) << 0) & 0x000000FF) 194 195 //***************************************************************************** 196 // 197 // JEDEC_CID2 - Coresight ROM Table. 198 // 199 //***************************************************************************** 200 // Coresight ROM Table, CID2. 201 #define AM_REG_JEDEC_CID2_CID_S 0 202 #define AM_REG_JEDEC_CID2_CID_M 0x000000FF 203 #define AM_REG_JEDEC_CID2_CID(n) (((uint32_t)(n) << 0) & 0x000000FF) 204 205 //***************************************************************************** 206 // 207 // JEDEC_CID3 - Coresight ROM Table. 208 // 209 //***************************************************************************** 210 // Coresight ROM Table, CID3. 211 #define AM_REG_JEDEC_CID3_CID_S 0 212 #define AM_REG_JEDEC_CID3_CID_M 0x000000FF 213 #define AM_REG_JEDEC_CID3_CID(n) (((uint32_t)(n) << 0) & 0x000000FF) 214 215 #endif // AM_REG_JEDEC_H 216