1;******************************************************************************
2;
3;! @file startup_keil.s
4;!
5;! @brief Definitions for Apollo2 interrupt handlers, the vector table, and the stack.
6;
7;******************************************************************************
8
9;******************************************************************************
10;
11; Copyright (c) 2017, Ambiq Micro
12; All rights reserved.
13;
14; Redistribution and use in source and binary forms, with or without
15; modification, are permitted provided that the following conditions are met:
16;
17; 1. Redistributions of source code must retain the above copyright notice,
18; this list of conditions and the following disclaimer.
19;
20; 2. Redistributions in binary form must reproduce the above copyright
21; notice, this list of conditions and the following disclaimer in the
22; documentation and/or other materials provided with the distribution.
23;
24; 3. Neither the name of the copyright holder nor the names of its
25; contributors may be used to endorse or promote products derived from this
26; software without specific prior written permission.
27;
28; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
32; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38; POSSIBILITY OF SUCH DAMAGE.
39;
40; This is part of revision 1.2.9 of the AmbiqSuite Development Package.
41;
42;******************************************************************************
43
44;******************************************************************************
45;
46; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
47;************************************************************************
48Stack   EQU     0x00001000
49
50;******************************************************************************
51;
52; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
53;
54;******************************************************************************
55Heap    EQU     0x00000000
56
57;******************************************************************************
58;
59; Allocate space for the stack.
60;
61;******************************************************************************
62        AREA    STACK, NOINIT, READWRITE, ALIGN=3
63StackMem
64        SPACE   Stack
65__initial_sp
66
67;******************************************************************************
68;
69; Allocate space for the heap.
70;
71;******************************************************************************
72        AREA    HEAP, NOINIT, READWRITE, ALIGN=3
73__heap_base
74HeapMem
75        SPACE   Heap
76__heap_limit
77
78;******************************************************************************
79;
80; Indicate that the code in this file preserves 8-byte alignment of the stack.
81;
82;******************************************************************************
83        PRESERVE8
84
85;******************************************************************************
86;
87; Place code into the reset code section.
88;
89;******************************************************************************
90        AREA    RESET, CODE, READONLY
91        THUMB
92
93;******************************************************************************
94;
95; The vector table.
96;
97;******************************************************************************
98;
99; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and
100; am_usagefault_isr does not work if am_fault_isr is defined externally.
101; Therefore, we'll explicitly use am_fault_isr in the table for those vectors.
102;
103
104        EXPORT  __Vectors
105__Vectors
106        DCD     StackMem + Stack            ; Top of Stack
107        DCD     Reset_Handler               ; Reset Handler
108        DCD     NMI_Handler                 ; NMI Handler
109        DCD     HardFault_Handler           ; Hard Fault Handler
110        DCD     MemoryManagement_Handler    ; The MPU fault handler
111        DCD     BusFault_Handler            ; The bus fault handler
112        DCD     UsageFault_Handler          ; The usage fault handler
113        DCD     0                           ; Reserved
114        DCD     0                           ; Reserved
115        DCD     0                           ; Reserved
116        DCD     0                           ; Reserved
117        DCD     SVC_Handler               	; SVCall handler
118        DCD     DebugMon_Handler            ; Debug monitor handler
119        DCD     0                           ; Reserved
120        DCD     PendSV_Handler              ; The PendSV handler
121        DCD     SysTick_Handler             ; The SysTick handler
122
123        ; Peripheral Interrupts
124        DCD     am_brownout_isr             ;  0: Reserved
125        DCD     am_watchdog_isr             ;  1: Reserved
126        DCD     am_clkgen_isr               ;  2: CLKGEN
127        DCD     am_vcomp_isr                ;  3: Voltage Comparator
128        DCD     am_ioslave_ios_isr          ;  4: I/O Slave general
129        DCD     am_ioslave_acc_isr          ;  5: I/O Slave access
130        DCD     am_iomaster0_isr            ;  6: I/O Master 0
131        DCD     am_iomaster1_isr            ;  7: I/O Master 1
132        DCD     am_iomaster2_isr            ;  8: I/O Master 2
133        DCD     am_iomaster3_isr            ;  9: I/O Master 3
134        DCD     am_iomaster4_isr            ; 10: I/O Master 4
135        DCD     am_iomaster5_isr            ; 11: I/O Master 5
136        DCD     am_gpio_isr                 ; 12: GPIO
137        DCD     am_ctimer_isr               ; 13: CTIMER
138        DCD     am_uart0_isr                ; 14: UART0
139        DCD     am_uart1_isr                ; 15: UART1
140        DCD     am_adc_isr                  ; 16: ADC
141        DCD     am_pdm_isr                  ; 17: PDM
142        DCD     am_stimer_isr               ; 18: SYSTEM TIMER
143        DCD     am_stimer_cmpr0_isr         ; 19: SYSTEM TIMER COMPARE0
144        DCD     am_stimer_cmpr1_isr         ; 20: SYSTEM TIMER COMPARE1
145        DCD     am_stimer_cmpr2_isr         ; 21: SYSTEM TIMER COMPARE2
146        DCD     am_stimer_cmpr3_isr         ; 22: SYSTEM TIMER COMPARE3
147        DCD     am_stimer_cmpr4_isr         ; 23: SYSTEM TIMER COMPARE4
148        DCD     am_stimer_cmpr5_isr         ; 24: SYSTEM TIMER COMPARE5
149        DCD     am_stimer_cmpr6_isr         ; 25: SYSTEM TIMER COMPARE6
150        DCD     am_stimer_cmpr7_isr         ; 26: SYSTEM TIMER COMPARE7
151        DCD     am_flash_isr                ; 27: FLASH
152        DCD     am_software0_isr            ; 28: SOFTWARE0
153        DCD     am_software1_isr            ; 29: SOFTWARE1
154        DCD     am_software2_isr            ; 30: SOFTWARE2
155        DCD     am_software3_isr            ; 31: SOFTWARE3
156
157__Vectors_End
158
159__Vectors_Size  EQU     __Vectors_End - __Vectors
160
161;******************************************************************************
162;
163; This is the code that gets called when the processor first starts execution
164; following a reset event.
165;
166;******************************************************************************
167Reset_Handler   PROC
168                EXPORT  Reset_Handler               [WEAK]
169                IMPORT  __main
170
171                ; Enable the FPU.
172                MOVW    R0, #0xED88
173                MOVT    R0, #0xE000
174                LDR     R1, [R0]
175                ORR     R1, #0x00F00000
176                STR     R1, [R0]
177                DSB
178                ISB
179
180                ; Branch to main.
181                LDR     R0, =__main
182                BX      R0
183
184                ENDP
185
186;******************************************************************************
187;
188; Weak Exception Handlers.
189;
190;******************************************************************************
191NMI_Handler     PROC
192                EXPORT  NMI_Handler                  [WEAK]
193                B       .
194                ENDP
195HardFault_Handler\
196                PROC
197                EXPORT  HardFault_Handler             [WEAK]
198                B       .
199                ENDP
200MemoryManagement_Handler\
201                PROC
202                EXPORT  MemoryManagement_Handler      [WEAK]
203                B       .
204                ENDP
205BusFault_Handler\
206                PROC
207                EXPORT  BusFault_Handler              [WEAK]
208                B       .
209                ENDP
210UsageFault_Handler\
211                PROC
212                EXPORT  UsageFault_Handler            [WEAK]
213                B       .
214                ENDP
215SVC_Handler     PROC
216                EXPORT  SVC_Handler               [WEAK]
217                B       .
218                ENDP
219DebugMon_Handler\
220                PROC
221                EXPORT  DebugMon_Handler          [WEAK]
222                B       .
223                ENDP
224PendSV_Handler  PROC
225                EXPORT  PendSV_Handler            [WEAK]
226                B       .
227                ENDP
228SysTick_Handler PROC
229                EXPORT  SysTick_Handler           [WEAK]
230                B       .
231                ENDP
232am_default_isr	PROC
233
234                EXPORT  am_brownout_isr             [WEAK]
235                EXPORT  am_watchdog_isr             [WEAK]
236                EXPORT  am_clkgen_isr               [WEAK]
237                EXPORT  am_vcomp_isr                [WEAK]
238                EXPORT  am_ioslave_ios_isr          [WEAK]
239                EXPORT  am_ioslave_acc_isr          [WEAK]
240                EXPORT  am_iomaster0_isr            [WEAK]
241                EXPORT  am_iomaster1_isr            [WEAK]
242                EXPORT  am_iomaster2_isr            [WEAK]
243                EXPORT  am_iomaster3_isr            [WEAK]
244                EXPORT  am_iomaster4_isr            [WEAK]
245                EXPORT  am_iomaster5_isr            [WEAK]
246                EXPORT  am_gpio_isr                 [WEAK]
247                EXPORT  am_ctimer_isr               [WEAK]
248                EXPORT  am_uart0_isr                [WEAK]
249                EXPORT  am_uart1_isr                [WEAK]
250				EXPORT  am_adc_isr                  [WEAK]
251                EXPORT  am_pdm_isr                  [WEAK]
252                EXPORT  am_stimer_isr               [WEAK]
253                EXPORT  am_stimer_cmpr0_isr         [WEAK]
254                EXPORT  am_stimer_cmpr1_isr         [WEAK]
255                EXPORT  am_stimer_cmpr2_isr         [WEAK]
256                EXPORT  am_stimer_cmpr3_isr         [WEAK]
257                EXPORT  am_stimer_cmpr4_isr         [WEAK]
258                EXPORT  am_stimer_cmpr5_isr         [WEAK]
259                EXPORT  am_stimer_cmpr6_isr         [WEAK]
260                EXPORT  am_stimer_cmpr7_isr         [WEAK]
261                EXPORT  am_flash_isr                [WEAK]
262                EXPORT  am_software0_isr            [WEAK]
263                EXPORT  am_software1_isr            [WEAK]
264                EXPORT  am_software2_isr            [WEAK]
265                EXPORT  am_software3_isr            [WEAK]
266
267am_brownout_isr
268am_watchdog_isr
269am_clkgen_isr
270am_vcomp_isr
271am_ioslave_ios_isr
272am_ioslave_acc_isr
273am_iomaster0_isr
274am_iomaster1_isr
275am_iomaster2_isr
276am_iomaster3_isr
277am_iomaster4_isr
278am_iomaster5_isr
279am_gpio_isr
280am_ctimer_isr
281am_uart0_isr
282am_uart1_isr
283am_adc_isr
284am_pdm_isr
285am_stimer_isr
286am_stimer_cmpr0_isr
287am_stimer_cmpr1_isr
288am_stimer_cmpr2_isr
289am_stimer_cmpr3_isr
290am_stimer_cmpr4_isr
291am_stimer_cmpr5_isr
292am_stimer_cmpr6_isr
293am_stimer_cmpr7_isr
294am_flash_isr
295am_software0_isr
296am_software1_isr
297am_software2_isr
298am_software3_isr
299
300                ; all device interrupts go here unless the weak label is over
301                ; ridden in the linker hard spin so the debugger will know it
302                ; was an unhandled interrupt request a come-from-buffer or
303                ; instruction trace hardware would sure be nice if you get here
304                B       .
305
306                ENDP
307
308;******************************************************************************
309;
310; Align the end of the section.
311;
312;******************************************************************************
313                ALIGN
314
315;******************************************************************************
316;
317; Initialization of the heap and stack.
318;
319;******************************************************************************
320                AREA    |.text|, CODE, READONLY
321
322;******************************************************************************
323;
324; User Initial Stack & Heap.
325;
326;******************************************************************************
327    IF :DEF: __MICROLIB
328        EXPORT  __initial_sp
329        EXPORT  __heap_base
330        EXPORT  __heap_limit
331    ELSE
332        IMPORT  __use_two_region_memory
333        EXPORT  __user_initial_stackheap
334__user_initial_stackheap PROC
335        LDR     R0, =HeapMem
336        LDR     R1, =(StackMem + Stack)
337        LDR     R2, =(HeapMem + Heap)
338        LDR     R3, =StackMem
339        BX      LR
340
341        ENDP
342
343    ENDIF
344
345;******************************************************************************
346;
347; Align the end of the section.
348;
349;******************************************************************************
350                ALIGN
351
352;******************************************************************************
353;
354; All Done
355;
356;******************************************************************************
357                END
358
359
360