1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2015-04-14 ArdaFu first version 9 */ 10 #ifndef __INTERRUPT_H__ 11 #define __INTERRUPT_H__ 12 13 #define INT_IRQ 0x00 14 #define INT_FIQ 0x01 15 16 17 // IRQ Source 18 #define INT_ARM_COMMRX 0 19 #define INT_ARM_COMMTX 1 20 #define INT_RTC 2 21 #define INT_GPIO0 3 22 #define INT_GPIO1 4 23 #define INT_GPIO2 5 24 #define INT_GPIO3 6 25 #define INT_GPIO4_IIS1 7 26 #define INT_USB0 8 27 #define INT_USB1 9 28 #define INT_USB0_DMA 10 29 #define INT_USB1_DMA 11 30 #define INT_MAC 12 31 #define INT_MAC_PMT 13 32 #define INT_NAND 14 33 #define INT_UART0 15 34 #define INT_UART1 16 35 #define INT_UART2 17 36 #define INT_UART3 18 37 #define INT_UART4 19 38 #define INT_UART5 20 39 #define INT_UART6 21 40 #define INT_UART7 22 41 #define INT_UART8 23 42 #define INT_UART9 24 43 #define INT_I2S0 25 44 #define INT_I2C0 26 45 #define INT_I2C1 27 46 #define INT_CAMIF 28 47 #define INT_TIMER0 29 48 #define INT_TIMER1 30 49 #define INT_TIMER2 31 50 #define INT_TIMER3 32 51 #define INT_ADC0 33 52 #define INT_DAC0 34 53 #define INT_USB0_RESUME_HOSTDISCONNECT 35 54 #define INT_USB0_VBUSVALID 36 55 #define INT_USB1_RESUME_HOSTDISCONNECT 37 56 #define INT_USB1_VBUSVALID 38 57 #define INT_DMA0_CH0 39 58 #define INT_DMA0_CH1 40 59 #define INT_DMA0_CH2 41 60 #define INT_DMA0_CH3 42 61 #define INT_DMA0_CH4 43 62 #define INT_DMA0_CH5 44 63 #define INT_DMA0_CH6 45 64 #define INT_DMA0_CH7 46 65 #define INT_DMA1_CH0 47 66 #define INT_DMA1_CH1 48 67 #define INT_DMA1_CH2 49 68 #define INT_DMA1_CH3 50 69 #define INT_DMA1_CH4 51 70 #define INT_DMA1_CH5 52 71 #define INT_DMA1_CH6 53 72 #define INT_DMA1_CH7 54 73 #define INT_WATCHDOG 55 74 #define INT_CAN0 56 75 #define INT_CAN1 57 76 #define INT_QEI 58 77 #define INT_MCPWM 59 78 #define INT_SPI0 60 79 #define INT_SPI1 61 80 #define INT_QUADSPI0 62 81 #define INT_SSP0 63 82 83 #endif 84