1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2015-04-14 ArdaFu first version
9 */
10
11 #include "asm9260t.h"
12 #include "rtthread.h"
13 #include "uart.h"
14
Hw_UartDisable(HW_USART_TypeDef * uartBase)15 void Hw_UartDisable(HW_USART_TypeDef* uartBase)
16 {
17 uartBase->INTR[R_CLR] = ASM_UART_INTR_RXIEN | ASM_UART_INTR_TXIEN | ASM_UART_INTR_RTIS;
18 uartBase->CTRL2[R_CLR] = ASM_UART_CTRL2_TXE | ASM_UART_CTRL2_RXE;
19 }
20
Hw_UartEnable(HW_USART_TypeDef * uartBase)21 void Hw_UartEnable(HW_USART_TypeDef* uartBase)
22 {
23 uartBase->CTRL2[R_CLR] = 0x0000C000UL; //clear CTSEN and RTSEN
24 uartBase->CTRL2[R_SET] = ASM_UART_CTRL2_TXE | ASM_UART_CTRL2_RXE | ASM_UART_CTRL2_USARTEN;
25 uartBase->INTR[R_SET] = ASM_UART_INTR_RXIEN | ASM_UART_INTR_RTIEN;
26 }
27
Hw_UartReset(HW_USART_TypeDef * uartBase)28 void Hw_UartReset(HW_USART_TypeDef* uartBase)
29 {
30 uartBase->CTRL0[R_CLR] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENABLE;
31 uartBase->CTRL0[R_SET] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENABLE;
32 }
33
Hw_UartConfig(HW_USART_TypeDef * uartBase,int baudRate,int dataBits,int stopBits,int parity)34 void Hw_UartConfig(HW_USART_TypeDef* uartBase,int baudRate, int dataBits, int stopBits,int parity)
35 {
36 rt_uint32_t mode = ASM_UART_LINECTRL_FEN;
37
38 switch (dataBits)
39 {
40 case 8:
41 mode |= ASM_UART_LINECTRL_WLEN8;
42 break;
43 case 7:
44 mode |= ASM_UART_LINECTRL_WLEN7;
45 break;
46 case 6:
47 mode |= ASM_UART_LINECTRL_WLEN6;
48 break;
49 case 5:
50 mode |= ASM_UART_LINECTRL_WLEN5;
51 break;
52 default:
53 mode |= ASM_UART_LINECTRL_WLEN8;
54 break;
55 }
56
57 switch (stopBits)
58 {
59 case 2:
60 mode |= ASM_UART_LINECTRL_STP2;
61 break;
62 case 1:
63 default:
64 break;
65 }
66
67 switch (parity)
68 {
69 case 1:
70 mode |= ASM_UART_LINECTRL_PEN;
71 break;
72 case 2:
73 mode |= ASM_UART_LINECTRL_PEN | ASM_UART_LINECTRL_EPS;
74 break;
75 case 0:
76 default:
77 break;
78 }
79 //16bit nBaudDivint
80 mode |= (((12000000 <<2 ) / baudRate) & UART_BAUD_DIVINT_MASK) << 10;
81 //6bit nNaudDivfrac
82 mode |= (((12000000 <<2 ) / baudRate) & UART_BAUD_DIVFRAC_MASK) << 8;
83
84
85 uartBase->LINECTRL[R_VAL] = mode;
86 }
87
Hw_UartInit(int index)88 void Hw_UartInit(int index)
89 {
90 // uart0 = bit11, uart9 = bit20
91 int ctrl_bit = index + 11;
92 outl(1UL<<ctrl_bit,REG_SET(HW_AHBCLKCTRL0)); //UART4 ENABLE bit15
93 outl(0x1, HW_UART0CLKDIV + index*4); //UART4 div 2
94 outl(1UL<<ctrl_bit,REG_CLR(HW_AHBCLKCTRL0)); //UART4 clk gate
95 outl(1UL<<ctrl_bit,REG_SET(HW_AHBCLKCTRL0)); //UART4 clk gate
96 outl(1UL<<ctrl_bit,REG_CLR(HW_PRESETCTRL0)); //UART4 reset
97 outl(1UL<<ctrl_bit,REG_SET(HW_PRESETCTRL0)); //UART4 reset
98 }
99