1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-04-12 shelton first version 9 */ 10 11 #include "board.h" 12 system_clock_config(void)13void system_clock_config(void) 14 { 15 /* reset crm */ 16 crm_reset(); 17 18 /* config flash psr register */ 19 flash_psr_set(FLASH_WAIT_CYCLE_4); 20 21 /* ensure system clock to highest, set power ldo output voltage to 1.3v */ 22 pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3); 23 24 crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); 25 26 /* wait till hext is ready */ 27 while(crm_hext_stable_wait() == ERROR) 28 { 29 } 30 31 /* config pll clock resource */ 32 crm_pll_config(CRM_PLL_SOURCE_HEXT, 72, 1, CRM_PLL_FR_2); 33 34 /* enable pll */ 35 crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); 36 37 /* wait till pll is ready */ 38 while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) 39 { 40 } 41 42 /* config ahbclk */ 43 crm_ahb_div_set(CRM_AHB_DIV_1); 44 45 /* config apb2clk, the maximum frequency of APB2 clock is 150 MHz */ 46 crm_apb2_div_set(CRM_APB2_DIV_1); 47 48 /* config apb1clk, the maximum frequency of APB1 clock is 120 MHz */ 49 crm_apb1_div_set(CRM_APB1_DIV_2); 50 51 /* enable auto step mode */ 52 crm_auto_step_mode_enable(TRUE); 53 54 /* select pll as system clock source */ 55 crm_sysclk_switch(CRM_SCLK_PLL); 56 57 /* wait till pll is used as system clock source */ 58 while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) 59 { 60 } 61 62 /* disable auto step mode */ 63 crm_auto_step_mode_enable(FALSE); 64 65 /* update system_core_clock global variable */ 66 system_core_clock_update(); 67 } 68