1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2023-04-08 shelton first version
9 */
10
11 #include "board.h"
12
system_clock_config(void)13 void system_clock_config(void)
14 {
15 /* reset crm */
16 crm_reset();
17
18 /* config flash psr register */
19 flash_psr_set(FLASH_WAIT_CYCLE_4);
20
21 /* ensure system clock to highest, set power ldo output voltage to 1.3v */
22 pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
23
24 crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
25
26 /* wait till hext is ready */
27 while(crm_hext_stable_wait() == ERROR)
28 {
29 }
30
31 /* config pll clock resource
32 common frequency config list: pll source selected hick or hext(8mhz)
33 _____________________________________________________________________________
34 | | | | | | | | |
35 | sysclk | 150 | 144 | 120 | 108 | 96 | 72 | 36 |
36 |________|_________|_________|_________|_________|_________|_________________|
37 | | | | | | | | |
38 |pll_ns | 75 | 72 | 120 | 108 | 96 | 72 | 72 |
39 | | | | | | | | |
40 |pll_ms | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
41 | | | | | | | | |
42 |pll_fr | FR_2 | FR_2 | FR_4 | FR_4 | FR_4 | FR_4 | FR_8 |
43 |________|_________|_________|_________|_________|_________|________|________|
44
45 if pll clock source selects hext with other frequency values, or configure pll to other
46 frequency values, please use the at32 new clock configuration tool for configuration. */
47 crm_pll_config(CRM_PLL_SOURCE_HEXT, 72, 1, CRM_PLL_FR_2);
48
49 /* enable pll */
50 crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
51
52 /* wait till pll is ready */
53 while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
54 {
55 }
56
57 /* config ahbclk */
58 crm_ahb_div_set(CRM_AHB_DIV_1);
59
60 /* config apb2clk, the maximum frequency of APB2 clock is 150 MHz */
61 crm_apb2_div_set(CRM_APB2_DIV_1);
62
63 /* config apb1clk, the maximum frequency of APB1 clock is 120 MHz */
64 crm_apb1_div_set(CRM_APB1_DIV_2);
65
66 /* enable auto step mode */
67 crm_auto_step_mode_enable(TRUE);
68
69 /* select pll as system clock source */
70 crm_sysclk_switch(CRM_SCLK_PLL);
71
72 /* wait till pll is used as system clock source */
73 while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
74 {
75 }
76
77 /* disable auto step mode */
78 crm_auto_step_mode_enable(FALSE);
79
80 /* update system_core_clock global variable */
81 system_core_clock_update();
82 }
83