1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2023-01-31 shelton first version 9 */ 10 11 #include "board.h" 12 system_clock_config(void)13void system_clock_config(void) 14 { 15 /* config flash psr register */ 16 flash_psr_set(FLASH_WAIT_CYCLE_2); 17 18 /* reset crm */ 19 crm_reset(); 20 21 crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); 22 23 /* wait till hext is ready */ 24 while(crm_hext_stable_wait() == ERROR) 25 { 26 } 27 28 /* config pll clock resource */ 29 crm_pll_config(CRM_PLL_SOURCE_HEXT, CRM_PLL_MULT_12); 30 31 /* enable pll */ 32 crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); 33 34 /* wait till pll is ready */ 35 while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) 36 { 37 } 38 39 /* config ahbclk */ 40 crm_ahb_div_set(CRM_AHB_DIV_1); 41 42 /* config apb2clk, the maximum frequency of APB1/APB2 clock is 96 MHz */ 43 crm_apb2_div_set(CRM_APB2_DIV_1); 44 45 /* config apb1clk, the maximum frequency of APB1/APB2 clock is 96 MHz */ 46 crm_apb1_div_set(CRM_APB1_DIV_1); 47 48 /* select pll as system clock source */ 49 crm_sysclk_switch(CRM_SCLK_PLL); 50 51 /* wait till pll is used as system clock source */ 52 while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) 53 { 54 } 55 56 /* update system_core_clock global variable */ 57 system_core_clock_update(); 58 } 59