1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-12-28 shelton first version 9 */ 10 11 #include "board.h" 12 system_clock_config(void)13void system_clock_config(void) 14 { 15 /* reset crm */ 16 crm_reset(); 17 18 /* set the flash clock divider */ 19 flash_psr_set(FLASH_WAIT_CYCLE_5); 20 21 /* enable pwc periph clock */ 22 crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); 23 24 /* config ldo voltage */ 25 pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3); 26 27 crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); 28 29 /* wait till hext is ready */ 30 while(crm_hext_stable_wait() == ERROR) 31 { 32 } 33 34 /* config pll clock resource */ 35 crm_pll_config(CRM_PLL_SOURCE_HEXT, 96, 1, CRM_PLL_FP_4); 36 37 /* config pllu divider */ 38 crm_pllu_div_set(CRM_PLL_FU_16); 39 40 /* pllu enable */ 41 crm_pllu_output_set(TRUE); 42 43 /* enable pll */ 44 crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); 45 46 /* wait till pll is ready */ 47 while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) 48 { 49 } 50 51 /* config ahbclk */ 52 crm_ahb_div_set(CRM_AHB_DIV_1); 53 54 /* config apb3clk */ 55 crm_apb3_div_set(CRM_APB3_DIV_4); 56 57 /* config apb2clk */ 58 crm_apb2_div_set(CRM_APB2_DIV_1); 59 60 /* config apb1clk */ 61 crm_apb1_div_set(CRM_APB1_DIV_1); 62 63 /* enable auto step mode */ 64 crm_auto_step_mode_enable(TRUE); 65 66 /* select pll as system clock source */ 67 crm_sysclk_switch(CRM_SCLK_PLL); 68 69 /* wait till pll is used as system clock source */ 70 while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) 71 { 72 } 73 74 /* disable auto step mode */ 75 crm_auto_step_mode_enable(FALSE); 76 77 /* update system_core_clock global variable */ 78 system_core_clock_update(); 79 } 80