1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2024-08-30 shelton first version
9 */
10
11 #include "board.h"
12
system_clock_config(void)13 void system_clock_config(void)
14 {
15 /* reset crm */
16 crm_reset();
17
18 /* config flash psr register */
19 flash_psr_set(FLASH_WAIT_CYCLE_5);
20
21 /* enable pwc periph clock */
22 crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
23
24 /* set power ldo output voltage to 1.3v */
25 pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
26
27 crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
28
29 /* wait till hext is ready */
30 while(crm_hext_stable_wait() == ERROR)
31 {
32 }
33
34 /* if pll parameter has changed, please use the AT32_New_Clock_Configuration tool for new configuration. */
35 crm_pll_config(CRM_PLL_SOURCE_HEXT, 90, 1, CRM_PLL_FR_4);
36
37 /* enable pll */
38 crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
39
40 /* wait till pll is ready */
41 while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
42 {
43 }
44
45 /* config ahbclk */
46 crm_ahb_div_set(CRM_AHB_DIV_1);
47
48 /* config apb3clk, the maximum frequency of APB3 clock is 90 MHz */
49 crm_apb3_div_set(CRM_APB3_DIV_4);
50
51 /* config apb2clk, the maximum frequency of APB2 clock is 180 MHz */
52 crm_apb2_div_set(CRM_APB2_DIV_1);
53
54 /* config apb1clk, the maximum frequency of APB1 clock is 180 MHz */
55 crm_apb1_div_set(CRM_APB1_DIV_1);
56
57 /* enable auto step mode */
58 crm_auto_step_mode_enable(TRUE);
59
60 /* select pll as system clock source */
61 crm_sysclk_switch(CRM_SCLK_PLL);
62
63 /* wait till pll is used as system clock source */
64 while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
65 {
66 }
67
68 /* disable auto step mode */
69 crm_auto_step_mode_enable(FALSE);
70
71 /* update system_core_clock global variable */
72 system_core_clock_update();
73 }
74