1 /**************************************************************************//**
2 * @file core_cm0plus.h
3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4 * @version V5.1.0
5 * @date 04. April 2023
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_CM0PLUS_H_GENERIC
32 #define __CORE_CM0PLUS_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex-M0+
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM0+ definitions */
66 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
69 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75 */
76 #define __FPU_USED 0U
77
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_FP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88 #elif defined (__ti__)
89 #if defined __ARM_FP
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93 #elif defined ( __GNUC__ )
94 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98 #elif defined ( __ICCARM__ )
99 #if defined __ARMVFP__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103 #elif defined ( __TI_ARM__ )
104 #if defined __TI_VFP_SUPPORT__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108 #elif defined ( __TASKING__ )
109 #if defined __FPU_VFP__
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113 #elif defined ( __CSMC__ )
114 #if ( __CSMC__ & 0x400U)
115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
116 #endif
117
118 #endif
119
120 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
121
122
123 #ifdef __cplusplus
124 }
125 #endif
126
127 #endif /* __CORE_CM0PLUS_H_GENERIC */
128
129 #ifndef __CMSIS_GENERIC
130
131 #ifndef __CORE_CM0PLUS_H_DEPENDANT
132 #define __CORE_CM0PLUS_H_DEPENDANT
133
134 #ifdef __cplusplus
135 extern "C" {
136 #endif
137
138 /* check device defines and use defaults */
139 #if defined __CHECK_DEVICE_DEFINES
140 #ifndef __CM0PLUS_REV
141 #define __CM0PLUS_REV 0x0000U
142 #warning "__CM0PLUS_REV not defined in device header file; using default!"
143 #endif
144
145 #ifndef __MPU_PRESENT
146 #define __MPU_PRESENT 0U
147 #warning "__MPU_PRESENT not defined in device header file; using default!"
148 #endif
149
150 #ifndef __VTOR_PRESENT
151 #define __VTOR_PRESENT 0U
152 #warning "__VTOR_PRESENT not defined in device header file; using default!"
153 #endif
154
155 #ifndef __NVIC_PRIO_BITS
156 #define __NVIC_PRIO_BITS 2U
157 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
158 #endif
159
160 #ifndef __Vendor_SysTickConfig
161 #define __Vendor_SysTickConfig 0U
162 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
163 #endif
164 #endif
165
166 /* IO definitions (access restrictions to peripheral registers) */
167 /**
168 \defgroup CMSIS_glob_defs CMSIS Global Defines
169
170 <strong>IO Type Qualifiers</strong> are used
171 \li to specify the access to peripheral variables.
172 \li for automatic generation of peripheral register debug information.
173 */
174 #ifdef __cplusplus
175 #define __I volatile /*!< Defines 'read only' permissions */
176 #else
177 #define __I volatile const /*!< Defines 'read only' permissions */
178 #endif
179 #define __O volatile /*!< Defines 'write only' permissions */
180 #define __IO volatile /*!< Defines 'read / write' permissions */
181
182 /* following defines should be used for structure members */
183 #define __IM volatile const /*! Defines 'read only' structure member permissions */
184 #define __OM volatile /*! Defines 'write only' structure member permissions */
185 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
186
187 /*@} end of group Cortex-M0+ */
188
189
190
191 /*******************************************************************************
192 * Register Abstraction
193 Core Register contain:
194 - Core Register
195 - Core NVIC Register
196 - Core SCB Register
197 - Core SysTick Register
198 - Core MPU Register
199 ******************************************************************************/
200 /**
201 \defgroup CMSIS_core_register Defines and Type Definitions
202 \brief Type definitions and defines for Cortex-M processor based devices.
203 */
204
205 /**
206 \ingroup CMSIS_core_register
207 \defgroup CMSIS_CORE Status and Control Registers
208 \brief Core Register type definitions.
209 @{
210 */
211
212 /**
213 \brief Union type to access the Application Program Status Register (APSR).
214 */
215 typedef union
216 {
217 struct
218 {
219 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
220 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
221 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
222 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
223 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
224 } b; /*!< Structure used for bit access */
225 uint32_t w; /*!< Type used for word access */
226 } APSR_Type;
227
228 /* APSR Register Definitions */
229 #define APSR_N_Pos 31U /*!< APSR: N Position */
230 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
231
232 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
233 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
234
235 #define APSR_C_Pos 29U /*!< APSR: C Position */
236 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
237
238 #define APSR_V_Pos 28U /*!< APSR: V Position */
239 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
240
241
242 /**
243 \brief Union type to access the Interrupt Program Status Register (IPSR).
244 */
245 typedef union
246 {
247 struct
248 {
249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
250 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
251 } b; /*!< Structure used for bit access */
252 uint32_t w; /*!< Type used for word access */
253 } IPSR_Type;
254
255 /* IPSR Register Definitions */
256 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
257 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
258
259
260 /**
261 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
262 */
263 typedef union
264 {
265 struct
266 {
267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
268 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
269 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
270 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
271 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
272 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
273 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
274 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
275 } b; /*!< Structure used for bit access */
276 uint32_t w; /*!< Type used for word access */
277 } xPSR_Type;
278
279 /* xPSR Register Definitions */
280 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
281 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
282
283 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
284 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
285
286 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
287 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
288
289 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
290 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
291
292 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
293 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
294
295 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
296 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
297
298
299 /**
300 \brief Union type to access the Control Registers (CONTROL).
301 */
302 typedef union
303 {
304 struct
305 {
306 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
307 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
308 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
309 } b; /*!< Structure used for bit access */
310 uint32_t w; /*!< Type used for word access */
311 } CONTROL_Type;
312
313 /* CONTROL Register Definitions */
314 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
315 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
316
317 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
318 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
319
320 /*@} end of group CMSIS_CORE */
321
322
323 /**
324 \ingroup CMSIS_core_register
325 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
326 \brief Type definitions for the NVIC Registers
327 @{
328 */
329
330 /**
331 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
332 */
333 typedef struct
334 {
335 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
336 uint32_t RESERVED0[31U];
337 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
338 uint32_t RESERVED1[31U];
339 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
340 uint32_t RESERVED2[31U];
341 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
342 uint32_t RESERVED3[31U];
343 uint32_t RESERVED4[64U];
344 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
345 } NVIC_Type;
346
347 /*@} end of group CMSIS_NVIC */
348
349
350 /**
351 \ingroup CMSIS_core_register
352 \defgroup CMSIS_SCB System Control Block (SCB)
353 \brief Type definitions for the System Control Block Registers
354 @{
355 */
356
357 /**
358 \brief Structure type to access the System Control Block (SCB).
359 */
360 typedef struct
361 {
362 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
363 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
364 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
365 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
366 #else
367 uint32_t RESERVED0;
368 #endif
369 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
370 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
371 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
372 uint32_t RESERVED1;
373 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
374 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
375 } SCB_Type;
376
377 /* SCB CPUID Register Definitions */
378 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
379 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
380
381 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
382 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
383
384 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
385 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
386
387 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
388 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
389
390 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
391 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
392
393 /* SCB Interrupt Control State Register Definitions */
394 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
395 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
396
397 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
398 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
399
400 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
401 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
402
403 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
404 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
405
406 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
407 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
408
409 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
410 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
411
412 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
413 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
414
415 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
416 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
417
418 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
419 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
420
421 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
422 /* SCB Interrupt Control State Register Definitions */
423 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
424 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
425 #endif
426
427 /* SCB Application Interrupt and Reset Control Register Definitions */
428 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
429 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
430
431 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
432 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
433
434 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
435 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
436
437 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
438 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
439
440 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
441 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
442
443 /* SCB System Control Register Definitions */
444 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
445 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
446
447 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
448 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
449
450 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
451 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
452
453 /* SCB Configuration Control Register Definitions */
454 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
455 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
456
457 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
458 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
459
460 /* SCB System Handler Control and State Register Definitions */
461 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
462 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
463
464 /*@} end of group CMSIS_SCB */
465
466
467 /**
468 \ingroup CMSIS_core_register
469 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
470 \brief Type definitions for the System Timer Registers.
471 @{
472 */
473
474 /**
475 \brief Structure type to access the System Timer (SysTick).
476 */
477 typedef struct
478 {
479 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
480 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
481 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
482 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
483 } SysTick_Type;
484
485 /* SysTick Control / Status Register Definitions */
486 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
487 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
488
489 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
490 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
491
492 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
493 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
494
495 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
496 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
497
498 /* SysTick Reload Register Definitions */
499 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
500 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
501
502 /* SysTick Current Register Definitions */
503 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
504 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
505
506 /* SysTick Calibration Register Definitions */
507 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
508 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
509
510 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
511 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
512
513 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
514 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
515
516 /*@} end of group CMSIS_SysTick */
517
518 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
519 /**
520 \ingroup CMSIS_core_register
521 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
522 \brief Type definitions for the Memory Protection Unit (MPU)
523 @{
524 */
525
526 /**
527 \brief Structure type to access the Memory Protection Unit (MPU).
528 */
529 typedef struct
530 {
531 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
532 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
533 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
534 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
535 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
536 } MPU_Type;
537
538 #define MPU_TYPE_RALIASES 1U
539
540 /* MPU Type Register Definitions */
541 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
542 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
543
544 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
545 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
546
547 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
548 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
549
550 /* MPU Control Register Definitions */
551 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
552 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
553
554 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
555 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
556
557 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
558 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
559
560 /* MPU Region Number Register Definitions */
561 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
562 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
563
564 /* MPU Region Base Address Register Definitions */
565 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
566 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
567
568 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
569 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
570
571 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
572 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
573
574 /* MPU Region Attribute and Size Register Definitions */
575 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
576 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
577
578 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
579 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
580
581 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
582 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
583
584 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
585 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
586
587 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
588 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
589
590 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
591 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
592
593 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
594 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
595
596 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
597 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
598
599 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
600 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
601
602 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
603 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
604
605 /*@} end of group CMSIS_MPU */
606 #endif
607
608
609 /**
610 \ingroup CMSIS_core_register
611 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
612 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
613 Therefore they are not covered by the Cortex-M0+ header file.
614 @{
615 */
616 /*@} end of group CMSIS_CoreDebug */
617
618
619 /**
620 \ingroup CMSIS_core_register
621 \defgroup CMSIS_core_bitfield Core register bit field macros
622 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
623 @{
624 */
625
626 /**
627 \brief Mask and shift a bit field value for use in a register bit range.
628 \param[in] field Name of the register bit field.
629 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
630 \return Masked and shifted value.
631 */
632 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
633
634 /**
635 \brief Mask and shift a register value to extract a bit filed value.
636 \param[in] field Name of the register bit field.
637 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
638 \return Masked and shifted bit field value.
639 */
640 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
641
642 /*@} end of group CMSIS_core_bitfield */
643
644
645 /**
646 \ingroup CMSIS_core_register
647 \defgroup CMSIS_core_base Core Definitions
648 \brief Definitions for base addresses, unions, and structures.
649 @{
650 */
651
652 /* Memory mapping of Core Hardware */
653 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
654 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
655 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
656 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
657
658 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
659 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
660 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
661
662 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
663 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
664 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
665 #endif
666
667 /*@} */
668
669
670
671 /*******************************************************************************
672 * Hardware Abstraction Layer
673 Core Function Interface contains:
674 - Core NVIC Functions
675 - Core SysTick Functions
676 - Core Register Access Functions
677 ******************************************************************************/
678 /**
679 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
680 */
681
682
683
684 /* ########################## NVIC functions #################################### */
685 /**
686 \ingroup CMSIS_Core_FunctionInterface
687 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
688 \brief Functions that manage interrupts and exceptions via the NVIC.
689 @{
690 */
691
692 #ifdef CMSIS_NVIC_VIRTUAL
693 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
694 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
695 #endif
696 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
697 #else
698 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
699 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
700 #define NVIC_EnableIRQ __NVIC_EnableIRQ
701 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
702 #define NVIC_DisableIRQ __NVIC_DisableIRQ
703 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
704 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
705 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
706 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
707 #define NVIC_SetPriority __NVIC_SetPriority
708 #define NVIC_GetPriority __NVIC_GetPriority
709 #define NVIC_SystemReset __NVIC_SystemReset
710 #endif /* CMSIS_NVIC_VIRTUAL */
711
712 #ifdef CMSIS_VECTAB_VIRTUAL
713 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
714 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
715 #endif
716 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
717 #else
718 #define NVIC_SetVector __NVIC_SetVector
719 #define NVIC_GetVector __NVIC_GetVector
720 #endif /* (CMSIS_VECTAB_VIRTUAL) */
721
722 #define NVIC_USER_IRQ_OFFSET 16
723
724
725 /* The following EXC_RETURN values are saved the LR on exception entry */
726 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
727 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
728 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
729
730
731 /* Interrupt Priorities are WORD accessible only under Armv6-M */
732 /* The following MACROS handle generation of the register offset and byte masks */
733 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
734 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
735 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
736
737 #define __NVIC_SetPriorityGrouping(X) (void)(X)
738 #define __NVIC_GetPriorityGrouping() (0U)
739
740 /**
741 \brief Enable Interrupt
742 \details Enables a device specific interrupt in the NVIC interrupt controller.
743 \param [in] IRQn Device specific interrupt number.
744 \note IRQn must not be negative.
745 */
__NVIC_EnableIRQ(IRQn_Type IRQn)746 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
747 {
748 if ((int32_t)(IRQn) >= 0)
749 {
750 __COMPILER_BARRIER();
751 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
752 __COMPILER_BARRIER();
753 }
754 }
755
756
757 /**
758 \brief Get Interrupt Enable status
759 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
760 \param [in] IRQn Device specific interrupt number.
761 \return 0 Interrupt is not enabled.
762 \return 1 Interrupt is enabled.
763 \note IRQn must not be negative.
764 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)765 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
766 {
767 if ((int32_t)(IRQn) >= 0)
768 {
769 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
770 }
771 else
772 {
773 return(0U);
774 }
775 }
776
777
778 /**
779 \brief Disable Interrupt
780 \details Disables a device specific interrupt in the NVIC interrupt controller.
781 \param [in] IRQn Device specific interrupt number.
782 \note IRQn must not be negative.
783 */
__NVIC_DisableIRQ(IRQn_Type IRQn)784 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
785 {
786 if ((int32_t)(IRQn) >= 0)
787 {
788 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
789 __DSB();
790 __ISB();
791 }
792 }
793
794
795 /**
796 \brief Get Pending Interrupt
797 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
798 \param [in] IRQn Device specific interrupt number.
799 \return 0 Interrupt status is not pending.
800 \return 1 Interrupt status is pending.
801 \note IRQn must not be negative.
802 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)803 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
804 {
805 if ((int32_t)(IRQn) >= 0)
806 {
807 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
808 }
809 else
810 {
811 return(0U);
812 }
813 }
814
815
816 /**
817 \brief Set Pending Interrupt
818 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
819 \param [in] IRQn Device specific interrupt number.
820 \note IRQn must not be negative.
821 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)822 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
823 {
824 if ((int32_t)(IRQn) >= 0)
825 {
826 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
827 }
828 }
829
830
831 /**
832 \brief Clear Pending Interrupt
833 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
834 \param [in] IRQn Device specific interrupt number.
835 \note IRQn must not be negative.
836 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)837 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
838 {
839 if ((int32_t)(IRQn) >= 0)
840 {
841 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
842 }
843 }
844
845
846 /**
847 \brief Set Interrupt Priority
848 \details Sets the priority of a device specific interrupt or a processor exception.
849 The interrupt number can be positive to specify a device specific interrupt,
850 or negative to specify a processor exception.
851 \param [in] IRQn Interrupt number.
852 \param [in] priority Priority to set.
853 \note The priority cannot be set for every processor exception.
854 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)855 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
856 {
857 if ((int32_t)(IRQn) >= 0)
858 {
859 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
860 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
861 }
862 else
863 {
864 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
865 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
866 }
867 }
868
869
870 /**
871 \brief Get Interrupt Priority
872 \details Reads the priority of a device specific interrupt or a processor exception.
873 The interrupt number can be positive to specify a device specific interrupt,
874 or negative to specify a processor exception.
875 \param [in] IRQn Interrupt number.
876 \return Interrupt Priority.
877 Value is aligned automatically to the implemented priority bits of the microcontroller.
878 */
__NVIC_GetPriority(IRQn_Type IRQn)879 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
880 {
881
882 if ((int32_t)(IRQn) >= 0)
883 {
884 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
885 }
886 else
887 {
888 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
889 }
890 }
891
892
893 /**
894 \brief Encode Priority
895 \details Encodes the priority for an interrupt with the given priority group,
896 preemptive priority value, and subpriority value.
897 In case of a conflict between priority grouping and available
898 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
899 \param [in] PriorityGroup Used priority group.
900 \param [in] PreemptPriority Preemptive priority value (starting from 0).
901 \param [in] SubPriority Subpriority value (starting from 0).
902 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
903 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)904 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
905 {
906 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
907 uint32_t PreemptPriorityBits;
908 uint32_t SubPriorityBits;
909
910 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
911 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
912
913 return (
914 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
915 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
916 );
917 }
918
919
920 /**
921 \brief Decode Priority
922 \details Decodes an interrupt priority value with a given priority group to
923 preemptive priority value and subpriority value.
924 In case of a conflict between priority grouping and available
925 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
926 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
927 \param [in] PriorityGroup Used priority group.
928 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
929 \param [out] pSubPriority Subpriority value (starting from 0).
930 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)931 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
932 {
933 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
934 uint32_t PreemptPriorityBits;
935 uint32_t SubPriorityBits;
936
937 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
938 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
939
940 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
941 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
942 }
943
944
945 /**
946 \brief Set Interrupt Vector
947 \details Sets an interrupt vector in SRAM based interrupt vector table.
948 The interrupt number can be positive to specify a device specific interrupt,
949 or negative to specify a processor exception.
950 VTOR must been relocated to SRAM before.
951 If VTOR is not present address 0 must be mapped to SRAM.
952 \param [in] IRQn Interrupt number
953 \param [in] vector Address of interrupt handler function
954 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)955 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
956 {
957 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
958 uint32_t *vectors = (uint32_t *)SCB->VTOR;
959 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
960 #else
961 uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
962 *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
963 #endif
964 /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
965 }
966
967
968 /**
969 \brief Get Interrupt Vector
970 \details Reads an interrupt vector from interrupt vector table.
971 The interrupt number can be positive to specify a device specific interrupt,
972 or negative to specify a processor exception.
973 \param [in] IRQn Interrupt number.
974 \return Address of interrupt handler function
975 */
__NVIC_GetVector(IRQn_Type IRQn)976 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
977 {
978 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
979 uint32_t *vectors = (uint32_t *)SCB->VTOR;
980 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
981 #else
982 uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
983 return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
984 #endif
985 }
986
987
988 /**
989 \brief System Reset
990 \details Initiates a system reset request to reset the MCU.
991 */
__NVIC_SystemReset(void)992 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
993 {
994 __DSB(); /* Ensure all outstanding memory accesses included
995 buffered write are completed before reset */
996 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
997 SCB_AIRCR_SYSRESETREQ_Msk);
998 __DSB(); /* Ensure completion of memory access */
999
1000 for(;;) /* wait until reset */
1001 {
1002 __NOP();
1003 }
1004 }
1005
1006 /*@} end of CMSIS_Core_NVICFunctions */
1007
1008 /* ########################## MPU functions #################################### */
1009
1010 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1011
1012 #include "mpu_armv7.h"
1013
1014 #endif
1015
1016 /* ########################## FPU functions #################################### */
1017 /**
1018 \ingroup CMSIS_Core_FunctionInterface
1019 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1020 \brief Function that provides FPU type.
1021 @{
1022 */
1023
1024 /**
1025 \brief get FPU type
1026 \details returns the FPU type
1027 \returns
1028 - \b 0: No FPU
1029 - \b 1: Single precision FPU
1030 - \b 2: Double + Single precision FPU
1031 */
SCB_GetFPUType(void)1032 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1033 {
1034 return 0U; /* No FPU */
1035 }
1036
1037
1038 /*@} end of CMSIS_Core_FpuFunctions */
1039
1040
1041
1042 /* ################################## SysTick function ############################################ */
1043 /**
1044 \ingroup CMSIS_Core_FunctionInterface
1045 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1046 \brief Functions that configure the System.
1047 @{
1048 */
1049
1050 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1051
1052 /**
1053 \brief System Tick Configuration
1054 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1055 Counter is in free running mode to generate periodic interrupts.
1056 \param [in] ticks Number of ticks between two interrupts.
1057 \return 0 Function succeeded.
1058 \return 1 Function failed.
1059 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1060 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1061 must contain a vendor-specific implementation of this function.
1062 */
SysTick_Config(uint32_t ticks)1063 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1064 {
1065 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1066 {
1067 return (1UL); /* Reload value impossible */
1068 }
1069
1070 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1071 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1072 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1073 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1074 SysTick_CTRL_TICKINT_Msk |
1075 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1076 return (0UL); /* Function successful */
1077 }
1078
1079 #endif
1080
1081 /*@} end of CMSIS_Core_SysTickFunctions */
1082
1083
1084
1085
1086 #ifdef __cplusplus
1087 }
1088 #endif
1089
1090 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
1091
1092 #endif /* __CMSIS_GENERIC */
1093