1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-05-16 shelton first version 9 * 2024-09-02 shelton add support phy lan8720 and yt8512 10 */ 11 12 #ifndef __DRV_EMAC_H__ 13 #define __DRV_EMAC_H__ 14 15 #include <rtthread.h> 16 #include <rthw.h> 17 #include <rtdevice.h> 18 #include "drv_common.h" 19 20 #define CRYSTAL_ON_PHY 0 /* phy does not with crystal */ 21 22 /* the phy basic control register */ 23 #define PHY_BASIC_CONTROL_REG 0x00U 24 #define PHY_RESET_MASK (1<<15) 25 #define PHY_AUTO_NEGOTIATION_MASK (1<<12) 26 27 /* the phy basic status register */ 28 #define PHY_BASIC_STATUS_REG 0x01U 29 #define PHY_LINKED_STATUS_MASK (1<<2) 30 #define PHY_AUTONEGO_COMPLETE_MASK (1<<5) 31 32 /* the phy id one register */ 33 #define PHY_ID1_REG 0x02U 34 /* the phy id two register */ 35 #define PHY_ID2_REG 0x03U 36 /* the phy auto-negotiate advertise register */ 37 #define PHY_AUTONEG_ADVERTISE_REG 0x04U 38 39 #if defined (PHY_USING_DM9162) 40 #define PHY_CONTROL_REG (0x00) /*!< basic mode control register */ 41 #define PHY_STATUS_REG (0x01) /*!< basic mode status register */ 42 #define PHY_SPECIFIED_CS_REG (0x11) /*!< specified configuration and status register */ 43 /* phy control register */ 44 #define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */ 45 #define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */ 46 #define PHY_RESET_BIT (0x8000) /*!< reset phy */ 47 /* phy status register */ 48 #define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */ 49 #define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */ 50 /* phy specified control/status register */ 51 #define PHY_FULL_DUPLEX_100MBPS_BIT (0x8000) /*!< full duplex 100 mbps */ 52 #define PHY_HALF_DUPLEX_100MBPS_BIT (0x4000) /*!< half duplex 100 mbps */ 53 #define PHY_FULL_DUPLEX_10MBPS_BIT (0x2000) /*!< full duplex 10 mbps */ 54 #define PHY_HALF_DUPLEX_10MBPS_BIT (0x1000) /*!< half duplex 10 mbps */ 55 #define PHY_DUPLEX_MODE (PHY_FULL_DUPLEX_100MBPS_BIT | PHY_FULL_DUPLEX_10MBPS_BIT) /*!< full duplex mode */ 56 #define PHY_SPEED_MODE (PHY_FULL_DUPLEX_10MBPS_BIT | PHY_HALF_DUPLEX_10MBPS_BIT) /*!< 10 mbps */ 57 /* the phy interrupt source flag register. */ 58 #define PHY_INTERRUPT_FLAG_REG 0x15U 59 /* the phy interrupt mask register. */ 60 #define PHY_INTERRUPT_MASK_REG 0x15U 61 #define PHY_INT_MASK 0 62 #elif defined (PHY_USING_DP83848) 63 #define PHY_CONTROL_REG (0x00) /*!< basic mode control register */ 64 #define PHY_STATUS_REG (0x01) /*!< basic mode status register */ 65 #define PHY_SPECIFIED_CS_REG (0x10) /*!< phy status register */ 66 /* phy control register */ 67 #define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */ 68 #define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */ 69 #define PHY_RESET_BIT (0x8000) /*!< reset phy */ 70 /* phy status register */ 71 #define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */ 72 #define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */ 73 74 #define PHY_DUPLEX_MODE (0x0004) /*!< full duplex mode */ 75 #define PHY_SPEED_MODE (0x0002) /*!< 10 mbps */ 76 77 /* the phy interrupt source flag register. */ 78 #define PHY_INTERRUPT_FLAG_REG 0x12U 79 #define PHY_LINK_CHANGE_FLAG (1<<13) 80 /* the phy interrupt control register. */ 81 #define PHY_INTERRUPT_CTRL_REG 0x11U 82 #define PHY_INTERRUPT_EN ((1<<0)|(1<<1)) 83 /* the phy interrupt mask register. */ 84 #define PHY_INTERRUPT_MASK_REG 0x12U 85 #define PHY_INT_MASK (1<<5) 86 #elif defined (PHY_USING_LAN8720) 87 #define PHY_CONTROL_REG (0x00) /*!< basic mode control register */ 88 #define PHY_STATUS_REG (0x01) /*!< basic mode status register */ 89 #define PHY_SPECIFIED_CS_REG (0x1F) /*!< specified configuration and status register */ 90 /* phy control register */ 91 #define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */ 92 #define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */ 93 #define PHY_RESET_BIT (0x8000) /*!< reset phy */ 94 /* phy status register */ 95 #define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */ 96 #define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */ 97 /* phy specified control/status register */ 98 #define PHY_FULL_DUPLEX_100MBPS_BIT (0x0018) /*!< full duplex 100 mbps */ 99 #define PHY_HALF_DUPLEX_100MBPS_BIT (0x0008) /*!< half duplex 100 mbps */ 100 #define PHY_FULL_DUPLEX_10MBPS_BIT (0x0014) /*!< full duplex 10 mbps */ 101 #define PHY_HALF_DUPLEX_10MBPS_BIT (0x0004) /*!< half duplex 10 mbps */ 102 #define PHY_DUPLEX_MODE (0x0100) /*!< full duplex mode */ 103 #define PHY_SPEED_MODE (0x2000) /*!< 100 mbps */ 104 /* the phy interrupt source flag register. */ 105 #define PHY_INTERRUPT_FLAG_REG 0x1DU 106 /* the phy interrupt mask register. */ 107 #define PHY_INTERRUPT_MASK_REG 0x1EU 108 #define PHY_INT_MASK (1<<4) 109 #elif defined (PHY_USING_YT8512) 110 #define PHY_CONTROL_REG (0x00) /*!< basic mode control register */ 111 #define PHY_STATUS_REG (0x01) /*!< basic mode status register */ 112 #define PHY_SPECIFIED_CS_REG (0x11) /*!< phy status register */ 113 /* phy control register */ 114 #define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */ 115 #define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */ 116 #define PHY_RESET_BIT (0x8000) /*!< reset phy */ 117 /* phy status register */ 118 #define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */ 119 #define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */ 120 121 #define PHY_DUPLEX_MODE (0x2000) /*!< full duplex mode */ 122 #define PHY_SPEED_MODE (0x4000) /*!< 100 mbps */ 123 124 /* the phy interrupt source flag register. */ 125 #define PHY_INTERRUPT_FLAG_REG 0x13U 126 #define PHY_LINK_CHANGE_FLAG (3<<10) 127 /* the phy interrupt mask register. */ 128 #define PHY_INTERRUPT_MASK_REG 0x12U 129 #define PHY_INT_MASK (3<<10) 130 #endif 131 132 #endif /* __DRV_EMAC_H__ */ 133