1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-05-16 shelton first version
9 * 2023-01-31 shelton add support f421/f425
10 * 2023-04-08 shelton add support f423
11 * 2023-10-18 shelton add support f402/f405
12 * 2024-04-12 shelton add support a403a and a423
13 * 2024-08-30 shelton add support m412 and m416
14 * 2024-12-18 shelton add support f455/f456 and f457
15 */
16
17 #include "drv_common.h"
18 #include "drv_gpio.h"
19
20 #ifdef RT_USING_PIN
21
22 #define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
23 #define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
24 #define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
25
26 #if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
27 defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425) || \
28 defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
29 defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
30 defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
31 defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
32 defined (SOC_SERIES_AT32F457)
33 #define PIN_ATPORTSOURCE(pin) (scfg_port_source_type)((uint8_t)(((pin) & 0xF0u) >> 4))
34 #define PIN_ATPINSOURCE(pin) (scfg_pins_source_type)((uint8_t)((pin) & 0xFu))
35 #else
36 #define PIN_ATPORTSOURCE(pin) (gpio_port_source_type)((uint8_t)(((pin) & 0xF0u) >> 4))
37 #define PIN_ATPINSOURCE(pin) (gpio_pins_source_type)((uint8_t)((pin) & 0xFu))
38 #endif
39
40 #define PIN_ATPORT(pin) ((gpio_type *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
41 #define PIN_ATPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
42
43 #if defined(GPIOZ)
44 #define __AT32_PORT_MAX 12u
45 #elif defined(GPIOK)
46 #define __AT32_PORT_MAX 11u
47 #elif defined(GPIOJ)
48 #define __AT32_PORT_MAX 10u
49 #elif defined(GPIOI)
50 #define __AT32_PORT_MAX 9u
51 #elif defined(GPIOH)
52 #define __AT32_PORT_MAX 8u
53 #elif defined(GPIOG)
54 #define __AT32_PORT_MAX 7u
55 #elif defined(GPIOF)
56 #define __AT32_PORT_MAX 6u
57 #elif defined(GPIOE)
58 #define __AT32_PORT_MAX 5u
59 #elif defined(GPIOD)
60 #define __AT32_PORT_MAX 4u
61 #elif defined(GPIOC)
62 #define __AT32_PORT_MAX 3u
63 #elif defined(GPIOB)
64 #define __AT32_PORT_MAX 2u
65 #elif defined(GPIOA)
66 #define __AT32_PORT_MAX 1u
67 #else
68 #define __AT32_PORT_MAX 0u
69 #error Unsupported AT32 GPIO peripheral.
70 #endif
71
72 #define PIN_ATPORT_MAX __AT32_PORT_MAX
73
74 #if defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425)
75 static const struct pin_irq_map pin_irq_map[] =
76 {
77 {GPIO_PINS_0, EXINT_LINE_0, EXINT1_0_IRQn},
78 {GPIO_PINS_1, EXINT_LINE_1, EXINT1_0_IRQn},
79 {GPIO_PINS_2, EXINT_LINE_2, EXINT3_2_IRQn},
80 {GPIO_PINS_3, EXINT_LINE_3, EXINT3_2_IRQn},
81 {GPIO_PINS_4, EXINT_LINE_4, EXINT15_4_IRQn},
82 {GPIO_PINS_5, EXINT_LINE_5, EXINT15_4_IRQn},
83 {GPIO_PINS_6, EXINT_LINE_6, EXINT15_4_IRQn},
84 {GPIO_PINS_7, EXINT_LINE_7, EXINT15_4_IRQn},
85 {GPIO_PINS_8, EXINT_LINE_8, EXINT15_4_IRQn},
86 {GPIO_PINS_9, EXINT_LINE_9, EXINT15_4_IRQn},
87 {GPIO_PINS_10, EXINT_LINE_10, EXINT15_4_IRQn},
88 {GPIO_PINS_11, EXINT_LINE_11, EXINT15_4_IRQn},
89 {GPIO_PINS_12, EXINT_LINE_12, EXINT15_4_IRQn},
90 {GPIO_PINS_13, EXINT_LINE_13, EXINT15_4_IRQn},
91 {GPIO_PINS_14, EXINT_LINE_14, EXINT15_4_IRQn},
92 {GPIO_PINS_15, EXINT_LINE_15, EXINT15_4_IRQn},
93 };
94 #else
95 static const struct pin_irq_map pin_irq_map[] =
96 {
97 {GPIO_PINS_0, EXINT_LINE_0, EXINT0_IRQn},
98 {GPIO_PINS_1, EXINT_LINE_1, EXINT1_IRQn},
99 {GPIO_PINS_2, EXINT_LINE_2, EXINT2_IRQn},
100 {GPIO_PINS_3, EXINT_LINE_3, EXINT3_IRQn},
101 {GPIO_PINS_4, EXINT_LINE_4, EXINT4_IRQn},
102 {GPIO_PINS_5, EXINT_LINE_5, EXINT9_5_IRQn},
103 {GPIO_PINS_6, EXINT_LINE_6, EXINT9_5_IRQn},
104 {GPIO_PINS_7, EXINT_LINE_7, EXINT9_5_IRQn},
105 {GPIO_PINS_8, EXINT_LINE_8, EXINT9_5_IRQn},
106 {GPIO_PINS_9, EXINT_LINE_9, EXINT9_5_IRQn},
107 {GPIO_PINS_10, EXINT_LINE_10, EXINT15_10_IRQn},
108 {GPIO_PINS_11, EXINT_LINE_11, EXINT15_10_IRQn},
109 {GPIO_PINS_12, EXINT_LINE_12, EXINT15_10_IRQn},
110 {GPIO_PINS_13, EXINT_LINE_13, EXINT15_10_IRQn},
111 {GPIO_PINS_14, EXINT_LINE_14, EXINT15_10_IRQn},
112 {GPIO_PINS_15, EXINT_LINE_15, EXINT15_10_IRQn},
113 };
114 #endif
115
116 static struct rt_pin_irq_hdr pin_irq_handler_tab[] =
117 {
118 {-1, 0, RT_NULL, RT_NULL},
119 {-1, 0, RT_NULL, RT_NULL},
120 {-1, 0, RT_NULL, RT_NULL},
121 {-1, 0, RT_NULL, RT_NULL},
122 {-1, 0, RT_NULL, RT_NULL},
123 {-1, 0, RT_NULL, RT_NULL},
124 {-1, 0, RT_NULL, RT_NULL},
125 {-1, 0, RT_NULL, RT_NULL},
126 {-1, 0, RT_NULL, RT_NULL},
127 {-1, 0, RT_NULL, RT_NULL},
128 {-1, 0, RT_NULL, RT_NULL},
129 {-1, 0, RT_NULL, RT_NULL},
130 {-1, 0, RT_NULL, RT_NULL},
131 {-1, 0, RT_NULL, RT_NULL},
132 {-1, 0, RT_NULL, RT_NULL},
133 {-1, 0, RT_NULL, RT_NULL},
134 };
135 static uint32_t pin_irq_enable_mask = 0;
136
137 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
138
at32_pin_get(const char * name)139 static rt_base_t at32_pin_get(const char *name)
140 {
141 rt_base_t pin = 0;
142 int hw_port_num, hw_pin_num = 0;
143 int i, name_len;
144
145 name_len = rt_strlen(name);
146
147 if ((name_len < 4) || (name_len >= 6))
148 {
149 return -RT_EINVAL;
150 }
151 if ((name[0] != 'P') || (name[2] != '.'))
152 {
153 return -RT_EINVAL;
154 }
155
156 if ((name[1] >= 'A') && (name[1] <= 'Z'))
157 {
158 hw_port_num = (int)(name[1] - 'A');
159 }
160 else
161 {
162 return -RT_EINVAL;
163 }
164
165 for (i = 3; i < name_len; i++)
166 {
167 hw_pin_num *= 10;
168 hw_pin_num += name[i] - '0';
169 }
170
171 pin = PIN_NUM(hw_port_num, hw_pin_num);
172
173 return pin;
174 }
175
at32_pin_write(rt_device_t dev,rt_base_t pin,rt_uint8_t value)176 static void at32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
177 {
178 gpio_type *gpio_port;
179
180 uint16_t gpio_pin;
181 if (PIN_PORT(pin) < PIN_ATPORT_MAX)
182 {
183 gpio_port = PIN_ATPORT(pin);
184 gpio_pin = PIN_ATPIN(pin);
185 }
186 else
187 {
188 return;
189 }
190 gpio_bits_write(gpio_port, gpio_pin, (confirm_state)value);
191 }
192
at32_pin_read(rt_device_t dev,rt_base_t pin)193 static rt_ssize_t at32_pin_read(rt_device_t dev, rt_base_t pin)
194 {
195 gpio_type *gpio_port;
196 uint16_t gpio_pin;
197 int value;
198
199 value = PIN_LOW;
200
201 if (PIN_PORT(pin) < PIN_ATPORT_MAX)
202 {
203 gpio_port = PIN_ATPORT(pin);
204 gpio_pin = PIN_ATPIN(pin);
205 value = gpio_input_data_bit_read(gpio_port, gpio_pin);
206 }
207 else
208 {
209 return -RT_EINVAL;
210 }
211
212 return value;
213 }
214
at32_pin_mode(rt_device_t dev,rt_base_t pin,rt_uint8_t mode)215 static void at32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
216 {
217 gpio_init_type gpio_init_struct;
218 gpio_type *gpio_port;
219 uint16_t gpio_pin;
220
221 if (PIN_PORT(pin) < PIN_ATPORT_MAX)
222 {
223 gpio_port = PIN_ATPORT(pin);
224 gpio_pin = PIN_ATPIN(pin);
225 }
226 else
227 {
228 return;
229 }
230
231 /* configure gpio_init_struct */
232 gpio_default_para_init(&gpio_init_struct);
233 gpio_init_struct.gpio_pins = gpio_pin;
234 gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
235 gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
236 gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
237 gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
238
239 if (mode == PIN_MODE_OUTPUT)
240 {
241 /* output setting */
242 gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
243 gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
244 gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
245 }
246 else if (mode == PIN_MODE_INPUT)
247 {
248 /* input setting: not pull. */
249 gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
250 gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
251 }
252 else if (mode == PIN_MODE_INPUT_PULLUP)
253 {
254 /* input setting: pull up. */
255 gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
256 gpio_init_struct.gpio_pull = GPIO_PULL_UP;
257 }
258 else if (mode == PIN_MODE_INPUT_PULLDOWN)
259 {
260 /* input setting: pull down. */
261 gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
262 gpio_init_struct.gpio_pull = GPIO_PULL_DOWN;
263 }
264 else if (mode == PIN_MODE_OUTPUT_OD)
265 {
266 /* output setting: od. */
267 gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
268 gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
269 }
270
271 gpio_init(gpio_port, &gpio_init_struct);
272 }
273
bit2bitno(rt_uint32_t bit)274 rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
275 {
276 rt_int32_t i;
277 for (i = 0; i < 32; i++)
278 {
279 if (((rt_uint32_t)0x01 << i) == bit)
280 {
281 return i;
282 }
283 }
284 return -1;
285 }
286
get_pin_irq_map(uint32_t pinbit)287 rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
288 {
289 rt_int32_t mapindex = bit2bitno(pinbit);
290 if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
291 {
292 return RT_NULL;
293 }
294 return &pin_irq_map[mapindex];
295 };
296
at32_pin_attach_irq(struct rt_device * device,rt_base_t pin,rt_uint8_t mode,void (* hdr)(void * args),void * args)297 static rt_err_t at32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
298 rt_uint8_t mode, void (*hdr)(void *args), void *args)
299 {
300 uint16_t gpio_pin;
301 rt_base_t level;
302 rt_int32_t irqindex = -1;
303
304 if (PIN_PORT(pin) < PIN_ATPORT_MAX)
305 {
306 gpio_pin = PIN_ATPIN(pin);
307 }
308 else
309 {
310 return -RT_EINVAL;
311 }
312
313 irqindex = bit2bitno(gpio_pin);
314 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
315 {
316 return -RT_EINVAL;
317 }
318
319 level = rt_hw_interrupt_disable();
320 if (pin_irq_handler_tab[irqindex].pin == pin &&
321 pin_irq_handler_tab[irqindex].hdr == hdr &&
322 pin_irq_handler_tab[irqindex].mode == mode &&
323 pin_irq_handler_tab[irqindex].args == args)
324 {
325 rt_hw_interrupt_enable(level);
326 return RT_EOK;
327 }
328 if (pin_irq_handler_tab[irqindex].pin != -1)
329 {
330 rt_hw_interrupt_enable(level);
331 return -RT_EBUSY;
332 }
333 pin_irq_handler_tab[irqindex].pin = pin;
334 pin_irq_handler_tab[irqindex].hdr = hdr;
335 pin_irq_handler_tab[irqindex].mode = mode;
336 pin_irq_handler_tab[irqindex].args = args;
337 rt_hw_interrupt_enable(level);
338
339 return RT_EOK;
340 }
341
at32_pin_dettach_irq(struct rt_device * device,rt_base_t pin)342 static rt_err_t at32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
343 {
344 uint16_t gpio_pin;
345 rt_base_t level;
346 rt_int32_t irqindex = -1;
347
348 if (PIN_PORT(pin) < PIN_ATPORT_MAX)
349 {
350 gpio_pin = PIN_ATPIN(pin);
351 }
352 else
353 {
354 return -RT_EINVAL;
355 }
356 irqindex = bit2bitno(gpio_pin);
357 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
358 {
359 return -RT_EINVAL;
360 }
361
362 level = rt_hw_interrupt_disable();
363 if (pin_irq_handler_tab[irqindex].pin == -1)
364 {
365 rt_hw_interrupt_enable(level);
366 return RT_EOK;
367 }
368 pin_irq_handler_tab[irqindex].pin = -1;
369 pin_irq_handler_tab[irqindex].hdr = RT_NULL;
370 pin_irq_handler_tab[irqindex].mode = 0;
371 pin_irq_handler_tab[irqindex].args = RT_NULL;
372 rt_hw_interrupt_enable(level);
373
374 return RT_EOK;
375 }
376
at32_pin_irq_enable(struct rt_device * device,rt_base_t pin,rt_uint8_t enabled)377 static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
378 rt_uint8_t enabled)
379 {
380 gpio_init_type gpio_init_struct;
381 exint_init_type exint_init_struct;
382 gpio_type *gpio_port;
383 uint16_t gpio_pin;
384 const struct pin_irq_map *irqmap;
385 rt_base_t level;
386 rt_int32_t irqindex = -1;
387
388 if (PIN_PORT(pin) < PIN_ATPORT_MAX)
389 {
390 gpio_port = PIN_ATPORT(pin);
391 gpio_pin = PIN_ATPIN(pin);
392 }
393 else
394 {
395 return -RT_EINVAL;
396 }
397
398 if (enabled == PIN_IRQ_ENABLE)
399 {
400 irqindex = bit2bitno(gpio_pin);
401 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
402 {
403 return -RT_EINVAL;
404 }
405
406 level = rt_hw_interrupt_disable();
407
408 if (pin_irq_handler_tab[irqindex].pin == -1)
409 {
410 rt_hw_interrupt_enable(level);
411 return -RT_EINVAL;
412 }
413
414 irqmap = &pin_irq_map[irqindex];
415
416 /* configure gpio_init_struct */
417 gpio_default_para_init(&gpio_init_struct);
418 exint_default_para_init(&exint_init_struct);
419
420 gpio_init_struct.gpio_pins = irqmap->pinbit;
421 gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
422 exint_init_struct.line_select = irqmap->pinbit;
423 exint_init_struct.line_mode = EXINT_LINE_INTERRUPT;
424 exint_init_struct.line_enable = TRUE;
425 switch (pin_irq_handler_tab[irqindex].mode)
426 {
427 case PIN_IRQ_MODE_RISING:
428 exint_init_struct.line_polarity = EXINT_TRIGGER_RISING_EDGE;
429 break;
430 case PIN_IRQ_MODE_FALLING:
431 exint_init_struct.line_polarity = EXINT_TRIGGER_FALLING_EDGE;
432 break;
433 case PIN_IRQ_MODE_RISING_FALLING:
434 exint_init_struct.line_polarity = EXINT_TRIGGER_BOTH_EDGE;
435 break;
436 }
437 gpio_init(gpio_port, &gpio_init_struct);
438
439 #if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
440 defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425) || \
441 defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
442 defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
443 defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
444 defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
445 defined (SOC_SERIES_AT32F457)
446 scfg_exint_line_config(PIN_ATPORTSOURCE(pin), PIN_ATPINSOURCE(pin));
447 #else
448 gpio_exint_line_config(PIN_ATPORTSOURCE(pin), PIN_ATPINSOURCE(pin));
449 #endif
450 exint_init(&exint_init_struct);
451
452 nvic_irq_enable(irqmap->irqno, 5, 0);
453 pin_irq_enable_mask |= irqmap->pinbit;
454
455 rt_hw_interrupt_enable(level);
456 }
457 else if (enabled == PIN_IRQ_DISABLE)
458 {
459 irqmap = get_pin_irq_map(gpio_pin);
460 if (irqmap == RT_NULL)
461 {
462 return -RT_EINVAL;
463 }
464
465 level = rt_hw_interrupt_disable();
466
467 pin_irq_enable_mask &= ~irqmap->pinbit;
468 exint_interrupt_enable(irqmap->lineno, FALSE);
469
470 if ((irqmap->pinbit >= GPIO_PINS_5) && (irqmap->pinbit <= GPIO_PINS_9))
471 {
472 if (!(pin_irq_enable_mask & (GPIO_PINS_5 | GPIO_PINS_6 | GPIO_PINS_7 | GPIO_PINS_8 | GPIO_PINS_9)))
473 {
474 nvic_irq_disable(irqmap->irqno);
475 }
476 }
477 else if ((irqmap->pinbit >= GPIO_PINS_10) && (irqmap->pinbit <= GPIO_PINS_15))
478 {
479 if (!(pin_irq_enable_mask & (GPIO_PINS_10 | GPIO_PINS_11 | GPIO_PINS_12 | GPIO_PINS_13 | GPIO_PINS_14 | GPIO_PINS_15)))
480 {
481 nvic_irq_disable(irqmap->irqno);
482 }
483 }
484 else
485 {
486 nvic_irq_disable(irqmap->irqno);
487 }
488 rt_hw_interrupt_enable(level);
489 }
490 else
491 {
492 return -RT_EINVAL;
493 }
494
495 return RT_EOK;
496 }
497
498 const static struct rt_pin_ops _at32_pin_ops =
499 {
500 at32_pin_mode,
501 at32_pin_write,
502 at32_pin_read,
503 at32_pin_attach_irq,
504 at32_pin_dettach_irq,
505 at32_pin_irq_enable,
506 at32_pin_get,
507 };
508
pin_irq_handler(int irqno)509 rt_inline void pin_irq_handler(int irqno)
510 {
511 exint_flag_clear(pin_irq_map[irqno].lineno);
512 if (pin_irq_handler_tab[irqno].hdr)
513 {
514 pin_irq_handler_tab[irqno].hdr(pin_irq_handler_tab[irqno].args);
515 }
516 }
517
gpio_exint_handler(uint16_t GPIO_Pin)518 void gpio_exint_handler(uint16_t GPIO_Pin)
519 {
520 pin_irq_handler(bit2bitno(GPIO_Pin));
521 }
522
523 #if defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425)
EXINT1_0_IRQHandler(void)524 void EXINT1_0_IRQHandler(void)
525 {
526 rt_interrupt_enter();
527 if (RESET != exint_flag_get(EXINT_LINE_0))
528 {
529 gpio_exint_handler(GPIO_PINS_0);
530 }
531 if (RESET != exint_flag_get(EXINT_LINE_1))
532 {
533 gpio_exint_handler(GPIO_PINS_1);
534 }
535 rt_interrupt_leave();
536 }
537
EXINT3_2_IRQHandler(void)538 void EXINT3_2_IRQHandler(void)
539 {
540 rt_interrupt_enter();
541 if (RESET != exint_flag_get(EXINT_LINE_2))
542 {
543 gpio_exint_handler(GPIO_PINS_2);
544 }
545 if (RESET != exint_flag_get(EXINT_LINE_3))
546 {
547 gpio_exint_handler(GPIO_PINS_3);
548 }
549 rt_interrupt_leave();
550 }
551
EXINT15_4_IRQHandler(void)552 void EXINT15_4_IRQHandler(void)
553 {
554 rt_interrupt_enter();
555 if (RESET != exint_flag_get(EXINT_LINE_4))
556 {
557 gpio_exint_handler(GPIO_PINS_4);
558 }
559 if (RESET != exint_flag_get(EXINT_LINE_5))
560 {
561 gpio_exint_handler(GPIO_PINS_5);
562 }
563 if (RESET != exint_flag_get(EXINT_LINE_6))
564 {
565 gpio_exint_handler(GPIO_PINS_6);
566 }
567 if (RESET != exint_flag_get(EXINT_LINE_7))
568 {
569 gpio_exint_handler(GPIO_PINS_7);
570 }
571 if (RESET != exint_flag_get(EXINT_LINE_8))
572 {
573 gpio_exint_handler(GPIO_PINS_8);
574 }
575 if (RESET != exint_flag_get(EXINT_LINE_9))
576 {
577 gpio_exint_handler(GPIO_PINS_9);
578 }
579 if (RESET != exint_flag_get(EXINT_LINE_10))
580 {
581 gpio_exint_handler(GPIO_PINS_10);
582 }
583 if (RESET != exint_flag_get(EXINT_LINE_11))
584 {
585 gpio_exint_handler(GPIO_PINS_11);
586 }
587 if (RESET != exint_flag_get(EXINT_LINE_12))
588 {
589 gpio_exint_handler(GPIO_PINS_12);
590 }
591 if (RESET != exint_flag_get(EXINT_LINE_13))
592 {
593 gpio_exint_handler(GPIO_PINS_13);
594 }
595 if (RESET != exint_flag_get(EXINT_LINE_14))
596 {
597 gpio_exint_handler(GPIO_PINS_14);
598 }
599 if (RESET != exint_flag_get(EXINT_LINE_15))
600 {
601 gpio_exint_handler(GPIO_PINS_15);
602 }
603 rt_interrupt_leave();
604 }
605 #else
EXINT0_IRQHandler(void)606 void EXINT0_IRQHandler(void)
607 {
608 rt_interrupt_enter();
609 gpio_exint_handler(GPIO_PINS_0);
610 rt_interrupt_leave();
611 }
612
EXINT1_IRQHandler(void)613 void EXINT1_IRQHandler(void)
614 {
615 rt_interrupt_enter();
616 gpio_exint_handler(GPIO_PINS_1);
617 rt_interrupt_leave();
618 }
619
EXINT2_IRQHandler(void)620 void EXINT2_IRQHandler(void)
621 {
622 rt_interrupt_enter();
623 gpio_exint_handler(GPIO_PINS_2);
624 rt_interrupt_leave();
625 }
626
EXINT3_IRQHandler(void)627 void EXINT3_IRQHandler(void)
628 {
629 rt_interrupt_enter();
630 gpio_exint_handler(GPIO_PINS_3);
631 rt_interrupt_leave();
632 }
633
EXINT4_IRQHandler(void)634 void EXINT4_IRQHandler(void)
635 {
636 rt_interrupt_enter();
637 gpio_exint_handler(GPIO_PINS_4);
638 rt_interrupt_leave();
639 }
640
EXINT9_5_IRQHandler(void)641 void EXINT9_5_IRQHandler(void)
642 {
643 rt_interrupt_enter();
644 if (RESET != exint_flag_get(EXINT_LINE_5))
645 {
646 gpio_exint_handler(GPIO_PINS_5);
647 }
648 if (RESET != exint_flag_get(EXINT_LINE_6))
649 {
650 gpio_exint_handler(GPIO_PINS_6);
651 }
652 if (RESET != exint_flag_get(EXINT_LINE_7))
653 {
654 gpio_exint_handler(GPIO_PINS_7);
655 }
656 if (RESET != exint_flag_get(EXINT_LINE_8))
657 {
658 gpio_exint_handler(GPIO_PINS_8);
659 }
660 if (RESET != exint_flag_get(EXINT_LINE_9))
661 {
662 gpio_exint_handler(GPIO_PINS_9);
663 }
664 rt_interrupt_leave();
665 }
666
EXINT15_10_IRQHandler(void)667 void EXINT15_10_IRQHandler(void)
668 {
669 rt_interrupt_enter();
670 if (RESET != exint_flag_get(EXINT_LINE_10))
671 {
672 gpio_exint_handler(GPIO_PINS_10);
673 }
674 if (RESET != exint_flag_get(EXINT_LINE_11))
675 {
676 gpio_exint_handler(GPIO_PINS_11);
677 }
678 if (RESET != exint_flag_get(EXINT_LINE_12))
679 {
680 gpio_exint_handler(GPIO_PINS_12);
681 }
682 if (RESET != exint_flag_get(EXINT_LINE_13))
683 {
684 gpio_exint_handler(GPIO_PINS_13);
685 }
686 if (RESET != exint_flag_get(EXINT_LINE_14))
687 {
688 gpio_exint_handler(GPIO_PINS_14);
689 }
690 if (RESET != exint_flag_get(EXINT_LINE_15))
691 {
692 gpio_exint_handler(GPIO_PINS_15);
693 }
694 rt_interrupt_leave();
695 }
696 #endif
697
rt_hw_pin_init(void)698 int rt_hw_pin_init(void)
699 {
700
701 #ifdef GPIOA
702 crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
703 #endif
704 #ifdef GPIOB
705 crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
706 #endif
707 #ifdef GPIOC
708 crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
709 #endif
710 #ifdef GPIOD
711 crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE);
712 #endif
713 #ifdef GPIOE
714 crm_periph_clock_enable(CRM_GPIOE_PERIPH_CLOCK, TRUE);
715 #endif
716 #ifdef GPIOF
717 crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE);
718 #endif
719 #ifdef GPIOG
720 crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK, TRUE);
721 #endif
722 #ifdef GPIOH
723 crm_periph_clock_enable(CRM_GPIOH_PERIPH_CLOCK, TRUE);
724 #endif
725
726 #if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
727 defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425) || \
728 defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
729 defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
730 defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
731 defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
732 defined (SOC_SERIES_AT32F457)
733 crm_periph_clock_enable(CRM_SCFG_PERIPH_CLOCK, TRUE);
734 #else
735 crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK, TRUE);
736 #endif
737
738 return rt_device_pin_register("pin", &_at32_pin_ops, RT_NULL);
739 }
740
741 INIT_BOARD_EXPORT(rt_hw_pin_init);
742
743 #endif /* RT_USING_PIN */
744