1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-04-08 shelton first version 9 */ 10 11 #ifndef __DRV_SDRAM_H__ 12 #define __DRV_SDRAM_H__ 13 14 #include <rtthread.h> 15 16 /* parameters for sdram peripheral */ 17 /* bank1 or bank2 */ 18 #define SDRAM_TARGET_BANK 1 19 /* at32f435 bank1:0xc0000000 bank2:0xd0000000 */ 20 #define SDRAM_BANK_ADDR ((uint32_t)0xC0000000) 21 /* data width: 8, 16, 32 */ 22 #define SDRAM_DATA_WIDTH 16 23 /* column bit numbers: 8, 9, 10, 11 */ 24 #define SDRAM_COLUMN_BITS 9 25 /* row bit numbers: 11, 12, 13 */ 26 #define SDRAM_ROW_BITS 13 27 /* cas latency clock number: 1, 2, 3 */ 28 #define SDRAM_CAS_LATENCY 3 29 /* read pipe delay: 0, 1, 2 */ 30 #define SDRAM_RPIPE_DELAY 1 31 /* clock divid: 2, 3 */ 32 #define SDCLOCK_PERIOD 3 33 /* refresh rate counter */ 34 /* counter = (refresh_count * 1000 * SDCLK) / row - 20 */ 35 /* counter = (64ms * 1000 * 144MHz) / 2^13 - 20 */ 36 #define SDRAM_REFRESH_COUNT ((uint32_t)0x0451) 37 #define SDRAM_SIZE ((uint32_t)0x1000000) 38 39 /* tmrd */ 40 #define LOADTOACTIVEDELAY XMC_DELAY_CYCLE_2 41 /* txsr */ 42 #define EXITSELFREFRESHDELAY XMC_DELAY_CYCLE_11 43 /* tras */ 44 #define SELFREFRESHTIME XMC_DELAY_CYCLE_7 45 /* trc */ 46 #define ROWCYCLEDELAY XMC_DELAY_CYCLE_9 47 /* twr */ 48 #define WRITERECOVERYTIME XMC_DELAY_CYCLE_2 49 /* trp */ 50 #define RPDELAY XMC_DELAY_CYCLE_3 51 /* trcd */ 52 #define RCDDELAY XMC_DELAY_CYCLE_3 53 54 /* memory mode register */ 55 #define SDRAM_BURST_LEN_1 ((uint16_t)0x0000) 56 #define SDRAM_BURST_LEN_2 ((uint16_t)0x0001) 57 #define SDRAM_BURST_LEN_4 ((uint16_t)0x0002) 58 #define SDRAM_BURST_LEN_8 ((uint16_t)0x0004) 59 #define SDRAM_BURST_SEQUENTIAL ((uint16_t)0x0000) 60 #define SDRAM_BURST_INTERLEAVED ((uint16_t)0x0008) 61 #define SDRAM_CAS_LATENCY_1 ((uint16_t)0x0010) 62 #define SDRAM_CAS_LATENCY_2 ((uint16_t)0x0020) 63 #define SDRAM_CAS_LATENCY_3 ((uint16_t)0x0030) 64 #define SDRAM_OPERATING_MODE_STANDARD ((uint16_t)0x0000) 65 #define SDRAM_WR_BURST_PROGRAMMED ((uint16_t)0x0000) 66 #define SDRAM_WR_BURST_SINGLE ((uint16_t)0x0200) 67 68 #ifdef __cplusplus 69 } 70 #endif 71 72 #endif /* __DRV_SDRAM_H__ */ 73