1#------------------------------------------------ 2# SDRAM initialization script for the AT91SAM9260 3#------------------------------------------------ 4 5#---------------------------------------------------------------------------- 6# _InitRSTC() 7# Function description 8# Initializes the RSTC (Reset controller). 9# This makes sense since the default is to not allow user resets, which makes it impossible to 10# apply a second RESET via J-Link 11#---------------------------------------------------------------------------- 12 13define _InitRSTC 14 # Allow user reset 15 set *0xFFFFFD08=0xA5000001 16end 17 18#---------------------------------------------------------------------------- 19# _MapRAMAt0() 20# Function description: Maps RAM at 0. 21#---------------------------------------------------------------------------- 22define _MapRAMAt0 23 echo "---------- SRAM remapped to 0 --------" \n 24 # Test and set Remap 25 set $__mac_i = *0xFFFFEF00 26 if ( (($__mac_i & 0x01) == 0) || (($__mac_i & 0x02) == 0)) 27 #toggle remap bits 28 set *0xFFFFEF00 = 0x03 29 else 30 echo "---------- The Remap is done ---------" \n 31 end 32end 33 34#---------------------------------------------------------------------------- 35# 36# _PllSetting() 37# Function description 38# Initializes the PMC. 39# 1. Enable the Main Oscillator 40# 2. Configure PLL 41# 3. Switch Master 42#---------------------------------------------------------------------------- 43 44define __PllSetting 45 if ((*(0xFFFFFC30)&0x3) != 0 ) 46 # Disable all PMC interrupt ( $$ JPP) 47 # AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) #(PMC) Interrupt Disable Register 48 # pPmc->PMC_IDR = 0xFFFFFFFF; 49 set *0xFFFFFC64 = 0xFFFFFFFF 50 # AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) #(PMC) Peripheral Clock Disable Register 51 set *0xFFFFFC14 = 0xFFFFFFFF 52 # Disable all clock only Processor clock is enabled. 53 set *0xFFFFFC04 = 0xFFFFFFFE 54 # AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) # (PMC) Master Clock Register 55 set *0xFFFFFC30 = 0x00000001 56 57 while ((*0xFFFFFC68 & 0x8) == 0) 58 end 59 60 61 # write reset value to PLLA and PLLB 62 # AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) # (PMC) PLL A Register 63 set *0xFFFFFC28 = 0x00003F00 64 65 # AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) # (PMC) PLL B Register 66 set *0xFFFFFC2C 0x00003F00 67 while ((*0xFFFFFC68 & 0x2) == 0) 68 end 69 while ((*0xFFFFFC68 & 0x4) == 0) 70 end 71 72 echo "---------- PLL Enable ---------------" \n 73 74 else 75 echo "---------- Core in SLOW CLOCK mode ---" \n 76 end 77end 78 79 80#---------------------------------------------------------------------------- 81# 82# __PllSetting100MHz() 83# Function description 84# Set core at 200 MHz and MCK at 100 MHz 85#---------------------------------------------------------------------------- 86 87define __PllSetting100MHz 88 echo "---------- PLL Set at 100 MHz --------" \n 89 90 #* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN )); 91 set *0xFFFFFC20=0x00004001 92 while ((*0xFFFFFC68 & 0x1) == 0) 93 end 94 # AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) # (PMC) Master Clock Register 95 set *0xFFFFFC30=0x00000001 96 while ((*0xFFFFFC68 & 0x8) == 0) 97 end 98 #* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) | 99 # (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9); 100 set *0xFFFFFC28=0x2060BF09 101 while ((*0xFFFFFC68 & 0x2) == 0) 102 end 103 # Configure PLLB 104 set *0xFFFFFC2C=0x207C3F0C 105 while ((*0xFFFFFC68 & 0x4) == 0) 106 end 107 #* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;; 108 set *0xFFFFFC30=0x00000102 109 while ((*0xFFFFFC68 & 0x8) == 0) 110 end 111end 112 113 114#---------------------------------------------------------------------------- 115# __initSDRAM() 116# Function description 117# Set SDRAM for works at 100 MHz 118#---------------------------------------------------------------------------- 119 120define __initSDRAM 121 122 # Configure EBI Chip select 123 # pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC; 124 # AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) # (CCFG) EBI Chip Select Assignement Register 125 set *0xFFFFEF1C=0x0001003A 126 127 # Configure PIOs 128 # AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31 129 # pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) # (PIOC) Select A Register 130 # pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) # (PIOC) Select B Register 131 # pPio->PIO_PDR = (periphAEnable | periphBEnable # Set in Periph mode 132 set *0xFFFFF870=0xFFFF0000 133 set *0xFFFFF874=0x00000000 134 set *0xFFFFF804=0xFFFF0000 135 136 # psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 | 137 # AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | 138 # AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ; 139 set *0xFFFFEA08=0x85227259 140 set $i = 0 141 while $i != 100 142 set $i += 1 143 end 144 # psdrc->SDRAMC_MR = 0x00000002; # Set PRCHG AL 145 set *0xFFFFEA00=0x00000002 146 # *AT91C_SDRAM = 0x00000000; # Perform PRCHG 147 set *0x20000000=0x00000000 148 set $i = 0 149 while $i != 100 150 set $i += 1 151 end 152 153 # psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 1st CBR 154 set *0xFFFFEA00=0x00000004 155 156 # *(AT91C_SDRAM+4) = 0x00000001; # Perform CBR 157 set *0x20000010=0x00000001 158 159 # psdrc->SDRAMC_MR = 0x00000004; # Set 2 CBR 160 set *0xFFFFEA00=0x00000004 161 # *(AT91C_SDRAM+8) = 0x00000002; # Perform CBR 162 set *0x20000020=0x00000002 163 164 # psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 3 CBR 165 set *0xFFFFEA00=0x00000004 166 # *(AT91C_SDRAM+0xc) = 0x00000003; # Perform CBR 167 set *0x20000030=0x00000003 168 169 # psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 4 CBR 170 set *0xFFFFEA00=0x00000004 171 # *(AT91C_SDRAM+0x10) = 0x00000004; # Perform CBR 172 set *0x20000040=0x00000004 173 174 # psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 5 CBR 175 set *0xFFFFEA00=0x00000004 176 # *(AT91C_SDRAM+0x14) = 0x00000005; # Perform CBR 177 set *0x20000050=0x00000005 178 179 # psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 6 CBR 180 set *0xFFFFEA00=0x00000004 181 # *(AT91C_SDRAM+0x18) = 0x00000006; # Perform CBR 182 set *0x20000060=0x00000006 183 184 # psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 7 CBR 185 set *0xFFFFEA00=0x00000004 186 # *(AT91C_SDRAM+0x1c) = 0x00000007; # Perform CBR 187 set *0x20000070=0x00000007 188 189 # psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 8 CBR 190 set *0xFFFFEA00=0x00000004 191 # *(AT91C_SDRAM+0x20) = 0x00000008; # Perform CBR 192 set *0x20000080=0x00000008 193 194 # psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; # Set LMR operation 195 set *0xFFFFEA00=0x00000003 196 # *(AT91C_SDRAM+0x24) = 0xcafedede; # Perform LMR burst=1, lat=2 197 set *0x20000090=0xCAFEDEDE 198 199 # psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; # Set Refresh Timer 390 for 25MHz (TR= 15.6 * F ) 200 set *0xFFFFEA04=0x000002B9 201 202 #* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; # Set Normal mode 203 set *0xFFFFEA00=0x00000000 204 205 #* *AT91C_SDRAM = 0x00000000; # Perform Normal mode 206 set *0x20000000=0x00000000 207 echo "---------- SDRAM Done at 100 MHz -----" \n 208end 209 210# Step1: Connect to the J-Link gdb server 211define reset 212 #target remote localhost:2331 213 monitor reset 214 215 # Step2: Reset peripheral (RSTC_CR) 216 #Init PLL 217 __PllSetting 218 __PllSetting100MHz 219 __initSDRAM 220 #* Set the RAM memory at 0x0020 0000 & 0x0000 0000 221 _MapRAMAt0 222 _InitRSTC 223 224 # Step3: Load file(eg. getting-started project) 225 load 226 227 mon reg pc=0x20000000 228 #info reg 229 230end