1// ---------------------------------------------------------
2//   ATMEL Microcontroller Software Support  -  ROUSSET  -
3// ---------------------------------------------------------
4// The software is delivered "AS IS" without warranty or
5// condition of any  kind, either express, implied or
6// statutory. This includes without limitation any warranty
7// or condition with respect to merchantability or fitness
8// for any particular purpose, or against the infringements of
9// intellectual property rights of others.
10// ---------------------------------------------------------
11//  File: SAM9_SDRAM.mac
12//  User setup file for CSPY debugger.
13//  1.1 08/Aug/06 jpp    : Creation
14//
15//  $Revision: 1.1.2.1 $
16//
17// ---------------------------------------------------------
18__var __mac_i;
19__var __mac_pt;
20
21/*********************************************************************
22*
23*       execUserReset() : JTAG set initially to Full Speed
24*/
25execUserReset()
26{
27    __message "------------------------------ execUserReset ---------------------------------";
28    _MapRAMAt0();                          //* Set the RAM memory at 0x00200000 & 0x00000000
29    __PllSetting();                        //* Init PLL
30    __PllSetting100MHz();
31    __message "-------------------------------Set PC Reset ----------------------------------";
32}
33
34/*********************************************************************
35*
36*       execUserPreload() : JTAG set initially to 32kHz
37*/
38execUserPreload()
39{
40    __message "------------------------------ execUserPreload ---------------------------------";
41    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
42    __writeMemory32(0xD3,0x98,"Register"); //*  Set CPSR
43    __PllSetting();                        //* Init PLL
44    __PllSetting100MHz();
45    __initSDRAM();                         //* Init SDRAM before load
46    _MapRAMAt0();                          //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
47    _InitRSTC();                           //* Enable User Reset to allow execUserReset() execution
48}
49
50
51
52/*********************************************************************
53*
54*       _InitRSTC()
55*
56* Function description
57*   Initializes the RSTC (Reset controller).
58*   This makes sense since the default is to not allow user resets, which makes it impossible to
59*   apply a second RESET via J-Link
60*/
61_InitRSTC() {
62    __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory");    // Allow user reset
63}
64
65
66/*********************************************************************
67*
68*       __initSDRAM()
69* Function description
70* Set SDRAM for works at 100 MHz
71*/
72__initSDRAM()
73{
74//* Configure EBI Chip select
75//    pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC | (1 << 16);
76// AT91C_CCFG_EBICSA ((AT91_REG *) 	0xFFFFEF1C) // (CCFG)  EBI Chip Select Assignement Register
77    __writeMemory32(0x0001003A,0xFFFFEF1C,"Memory");
78
79
80//*  Configure PIOs
81//*	AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
82// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
83// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR  ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
84// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
85    __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");
86    __writeMemory32(0x00000000,0xFFFFF874,"Memory");
87    __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");
88
89//* psdrc->SDRAMC_CR =  AT91C_SDRAMC_NC_9  | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |
90//  AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
91//  AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
92    __writeMemory32(0x85227259,0xFFFFEA08,"Memory");
93 __delay(1); //100
94//*	psdrc->SDRAMC_MR	= 0x00000002;		// Set PRCHG AL
95    __writeMemory32(0x00000002,0xFFFFEA00,"Memory");
96//*	*AT91C_SDRAM	= 0x00000000;			// Perform PRCHG
97    __writeMemory32(0x00000000,0x20000000,"Memory");
98 __delay(1); //100
99
100
101//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
102      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
103
104//*	*(AT91C_SDRAM+4)	= 0x00000001;	// Perform CBR
105    __writeMemory32(0x00000001,0x20000010,"Memory");
106
107//*	psdrc->SDRAMC_MR	= 0x00000004;		// Set 2 CBR
108     __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
109//*	*(AT91C_SDRAM+8)	= 0x00000002;	// Perform CBR
110     __writeMemory32(0x00000002,0x20000020,"Memory");
111
112//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 3 CBR
113      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
114//*	*(AT91C_SDRAM+0xc)	= 0x00000003;	// Perform CBR
115     __writeMemory32(0x00000003,0x20000030,"Memory");
116
117//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 4 CBR
118      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
119//*	*(AT91C_SDRAM+0x10)	= 0x00000004;	// Perform CBR
120     __writeMemory32(0x00000004,0x20000040,"Memory");
121
122//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 5 CBR
123      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
124//*	*(AT91C_SDRAM+0x14)	= 0x00000005;	// Perform CBR
125     __writeMemory32(0x00000005,0x20000050,"Memory");
126
127//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 6 CBR
128      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
129//*	*(AT91C_SDRAM+0x18)	= 0x00000006;	// Perform CBR
130     __writeMemory32(0x00000006,0x20000060,"Memory");
131
132//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 7 CBR
133      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
134//*	*(AT91C_SDRAM+0x1c)	= 0x00000007;	// Perform CBR
135     __writeMemory32(0x00000007,0x20000070,"Memory");
136
137//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 8 CBR
138      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
139//*	*(AT91C_SDRAM+0x20)	= 0x00000008;	// Perform CBR
140     __writeMemory32(0x00000008,0x20000080,"Memory");
141
142//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_LMR_CMD;		// Set LMR operation
143      __writeMemory32(0x00000003,0xFFFFEA00,"Memory");
144//*	*(AT91C_SDRAM+0x24)	= 0xcafedede;		// Perform LMR burst=1, lat=2
145     __writeMemory32(0xCAFEDEDE,0x20000090,"Memory");
146
147//*	psdrc->SDRAMC_TR	= (AT91C_MASTER_CLOCK * 7)/1000000;				// Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
148//									               // (F : system clock freq. MHz
149
150      __writeMemory32(0x000002B7,0xFFFFEA04,"Memory");
151
152//*	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_NORMAL_CMD;		// Set Normal mode
153      __writeMemory32(0x00000000,0xFFFFEA00,"Memory");
154
155//*	*AT91C_SDRAM	= 0x00000000;	// Perform Normal mode
156      __writeMemory32(0x00000000,0x20000000,"Memory");
157   __message "------------------------------- SDRAM Done at 100 MHz -------------------------------";
158
159}
160
161/*********************************************************************
162*
163*       _MapRAMAt0()
164* Function description
165* Remap RAM at 0
166*/
167_MapRAMAt0()
168{
169// AT91C_MATRIX_MRCR ((AT91_REG *) 	0xFFFFEF00) // (MATRIX)  Master Remp Control Register
170    __mac_i=__readMemory32(0xFFFFEF00,"Memory");
171    __message "----- AT91C_MATRIX_MRCR  : 0x",__mac_i:%X;
172
173    if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
174        __message "------------------------------- The Remap is NOT & REMAP ----------------------------";
175        __writeMemory32(0x00000003,0xFFFFEF00,"Memory");
176        __mac_i=__readMemory32(0xFFFFEF00,"Memory");
177        __message "----- AT91C_MATRIX_MRCR  : 0x",__mac_i:%X;
178    } else {
179        __message "------------------------------- The Remap is done -----------------------------------";
180    }
181}
182
183
184/*********************************************************************
185*
186*       __PllSetting()
187* Function description
188*   Initializes the PMC.
189*   1. Enable the Main Oscillator
190*   2. Configure PLL
191*   3. Switch Master
192*/
193__PllSetting()
194{
195     if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
196//* Disable all PMC interrupt ( $$ JPP)
197//* AT91C_PMC_IDR   ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
198//*    pPmc->PMC_IDR = 0xFFFFFFFF;
199    __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
200//* AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
201    __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
202// Disable all clock only Processor clock is enabled.
203    __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
204
205// AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
206    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
207    __delay(10); //10000
208
209// write reset value to PLLA and PLLB
210// AT91C_PMC_PLLAR ((AT91_REG *) 	0xFFFFFC28) // (PMC) PLL A Register
211    __writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
212
213// AT91C_PMC_PLLBR ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL B Register
214    __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
215    __delay(10); //10000
216
217   __message "------------------------------- PLL  Enable -----------------------------------------";
218   } else {
219   __message " ********* Core in SLOW CLOCK mode ********* "; }
220}
221
222
223/*********************************************************************
224*
225*       __PllSetting100MHz()
226* Function description
227*   Set core at 200 MHz and MCK at 100 MHz
228*/
229__PllSetting100MHz()
230{
231
232   __message "------------------------------- PLL Set at 100 MHz ----------------------------------";
233
234//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
235    __writeMemory32(0x00004001,0xFFFFFC20,"Memory");
236    __delay(10); //10000
237// AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
238    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
239    __delay(10); //10000
240//*   AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
241//    (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
242    __writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
243    __delay(10); //10000
244// AT91C_BASE_PMC->PMC_PLLBR = BOARD_USBDIV| BOARD_CKGR_PLLB | BOARD_PLLBCOUNT | BOARD_MULB| BOARD_DIVB;
245    __writeMemory32(0x207C3F0C,0xFFFFFC2C,"Memory");
246    __delay(10); //10000
247//*   AT91C_BASE_PMC->PMC_MCKR =  AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
248    __writeMemory32(0x00000102,0xFFFFFC30,"Memory");
249     __delay(10); //10000
250
251}
252
253