1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2011-07-25 weety first version
9 */
10
11 #include <rtthread.h>
12 #include <rthw.h>
13 #include <drivers/dev_mmcsd_core.h>
14 #include <at91sam926x.h>
15 #include "at91_mci.h"
16
17 #define USE_SLOT_B
18 //#define RT_MCI_DBG
19
20 #ifdef RT_MCI_DBG
21 #define mci_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
22 #else
23 #define mci_dbg(fmt, ...)
24 #endif
25
26 #define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
27
28 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
29 extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
30
31
32 #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
33 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
34 | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
35
36 #define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg))
37 #define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg))
38
39
40 #define REQ_ST_INIT (1U << 0)
41 #define REQ_ST_CMD (1U << 1)
42 #define REQ_ST_STOP (1U << 2)
43
44 struct at91_mci {
45 struct rt_mmcsd_host *host;
46 struct rt_mmcsd_req *req;
47 struct rt_mmcsd_cmd *cmd;
48 struct rt_timer timer;
49 //struct rt_semaphore sem_ack;
50 rt_uint32_t *buf;
51 rt_uint32_t current_status;
52 };
53
54 /*
55 * Reset the controller and restore most of the state
56 */
at91_reset_host()57 static void at91_reset_host()
58 {
59 rt_uint32_t mr;
60 rt_uint32_t sdcr;
61 rt_uint32_t dtor;
62 rt_uint32_t imr;
63 rt_uint32_t level;
64
65 level = rt_hw_interrupt_disable();
66
67 imr = at91_mci_read(AT91_MCI_IMR);
68
69 at91_mci_write(AT91_MCI_IDR, 0xffffffff);
70
71 /* save current state */
72 mr = at91_mci_read(AT91_MCI_MR) & 0x7fff;
73 sdcr = at91_mci_read(AT91_MCI_SDCR);
74 dtor = at91_mci_read(AT91_MCI_DTOR);
75
76 /* reset the controller */
77 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
78
79 /* restore state */
80 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
81 at91_mci_write(AT91_MCI_MR, mr);
82 at91_mci_write(AT91_MCI_SDCR, sdcr);
83 at91_mci_write(AT91_MCI_DTOR, dtor);
84 at91_mci_write(AT91_MCI_IER, imr);
85
86 /* make sure sdio interrupts will fire */
87 at91_mci_read(AT91_MCI_SR);
88 rt_hw_interrupt_enable(level);
89
90 }
91
92
93 /*
94 * Enable the controller
95 */
at91_mci_enable()96 static void at91_mci_enable()
97 {
98 rt_uint32_t mr;
99
100 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
101 at91_mci_write(AT91_MCI_IDR, 0xffffffff);
102 at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
103 mr = AT91_MCI_PDCMODE | 0x34a;
104
105 mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
106
107 at91_mci_write(AT91_MCI_MR, mr);
108
109 /* use Slot A or B (only one at same time) */
110 at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */
111 }
112
113 /*
114 * Disable the controller
115 */
at91_mci_disable()116 static void at91_mci_disable()
117 {
118 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
119 }
120
at91_timeout_timer(void * data)121 static void at91_timeout_timer(void *data)
122 {
123 struct at91_mci *mci;
124
125 mci = (struct at91_mci *)data;
126
127 if (mci->req)
128 {
129 rt_kprintf("Timeout waiting end of packet\n");
130
131 if (mci->current_status == REQ_ST_CMD)
132 {
133 if (mci->req->cmd && mci->req->data)
134 {
135 mci->req->data->err = -RT_ETIMEOUT;
136 }
137 else
138 {
139 if (mci->req->cmd)
140 mci->req->cmd->err = -RT_ETIMEOUT;
141 }
142 }
143 else if (mci->current_status == REQ_ST_STOP)
144 {
145 mci->req->stop->err = -RT_ETIMEOUT;
146 }
147
148 at91_reset_host();
149 mmcsd_req_complete(mci->host);
150 }
151 }
152
153 /*
154 * Prepare a dma read
155 */
at91_mci_init_dma_read(struct at91_mci * mci)156 static void at91_mci_init_dma_read(struct at91_mci *mci)
157 {
158 rt_uint8_t i;
159 struct rt_mmcsd_cmd *cmd;
160 struct rt_mmcsd_data *data;
161 rt_uint32_t length;
162
163 mci_dbg("pre dma read\n");
164
165 cmd = mci->cmd;
166 if (!cmd)
167 {
168 mci_dbg("no command\n");
169 return;
170 }
171
172 data = cmd->data;
173 if (!data)
174 {
175 mci_dbg("no data\n");
176 return;
177 }
178
179 for (i = 0; i < 1; i++)
180 {
181 /* Check to see if this needs filling */
182 if (i == 0)
183 {
184 if (at91_mci_read(AT91_PDC_RCR) != 0)
185 {
186 mci_dbg("Transfer active in current\n");
187 continue;
188 }
189 }
190 else {
191 if (at91_mci_read(AT91_PDC_RNCR) != 0)
192 {
193 mci_dbg("Transfer active in next\n");
194 continue;
195 }
196 }
197
198 length = data->blksize * data->blks;
199 mci_dbg("dma address = %08X, length = %d\n", data->buf, length);
200
201 if (i == 0)
202 {
203 at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf));
204 at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4);
205 }
206 else
207 {
208 at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf));
209 at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4);
210 }
211 }
212
213 mci_dbg("pre dma read done\n");
214 }
215
216 /*
217 * Send a command
218 */
at91_mci_send_command(struct at91_mci * mci,struct rt_mmcsd_cmd * cmd)219 static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd)
220 {
221 rt_uint32_t cmdr, mr;
222 rt_uint32_t block_length;
223 struct rt_mmcsd_data *data = cmd->data;
224 struct rt_mmcsd_host *host = mci->host;
225
226 rt_uint32_t blocks;
227 rt_uint32_t ier = 0;
228 rt_uint32_t length;
229
230 mci->cmd = cmd;
231
232 /* Needed for leaving busy state before CMD1 */
233 if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1))
234 {
235 mci_dbg("Clearing timeout\n");
236 at91_mci_write(AT91_MCI_ARGR, 0);
237 at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
238 while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
239 {
240 /* spin */
241 mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
242 }
243 }
244
245 cmdr = cmd->cmd_code;
246
247 if (resp_type(cmd) == RESP_NONE)
248 cmdr |= AT91_MCI_RSPTYP_NONE;
249 else
250 {
251 /* if a response is expected then allow maximum response latancy */
252 cmdr |= AT91_MCI_MAXLAT;
253 /* set 136 bit response for R2, 48 bit response otherwise */
254 if (resp_type(cmd) == RESP_R2)
255 cmdr |= AT91_MCI_RSPTYP_136;
256 else
257 cmdr |= AT91_MCI_RSPTYP_48;
258 }
259
260 if (data)
261 {
262
263 block_length = data->blksize;
264 blocks = data->blks;
265
266 /* always set data start - also set direction flag for read */
267 if (data->flags & DATA_DIR_READ)
268 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
269 else if (data->flags & DATA_DIR_WRITE)
270 cmdr |= AT91_MCI_TRCMD_START;
271
272 if (data->flags & DATA_STREAM)
273 cmdr |= AT91_MCI_TRTYP_STREAM;
274 if (data->blks > 1)
275 cmdr |= AT91_MCI_TRTYP_MULTIPLE;
276 }
277 else
278 {
279 block_length = 0;
280 blocks = 0;
281 }
282
283 /*if (cmd->cmd_code == GO_IDLE_STATE)
284 {
285 cmdr |= AT91_MCI_SPCMD_INIT;
286 }*/
287
288 if (cmd->cmd_code == STOP_TRANSMISSION)
289 cmdr |= AT91_MCI_TRCMD_STOP;
290
291 if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN)
292 cmdr |= AT91_MCI_OPDCMD;
293
294 /*
295 * Set the arguments and send the command
296 */
297 mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
298 cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
299
300 if (!data)
301 {
302 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
303 at91_mci_write(AT91_PDC_RPR, 0);
304 at91_mci_write(AT91_PDC_RCR, 0);
305 at91_mci_write(AT91_PDC_RNPR, 0);
306 at91_mci_write(AT91_PDC_RNCR, 0);
307 at91_mci_write(AT91_PDC_TPR, 0);
308 at91_mci_write(AT91_PDC_TCR, 0);
309 at91_mci_write(AT91_PDC_TNPR, 0);
310 at91_mci_write(AT91_PDC_TNCR, 0);
311 ier = AT91_MCI_CMDRDY;
312 }
313 else
314 {
315 /* zero block length and PDC mode */
316 mr = at91_mci_read(AT91_MCI_MR) & 0x5fff;
317 mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0;
318 mr |= (block_length << 16);
319 mr |= AT91_MCI_PDCMODE;
320 at91_mci_write(AT91_MCI_MR, mr);
321
322 at91_mci_write(AT91_MCI_BLKR,
323 AT91_MCI_BLKR_BCNT(blocks) |
324 AT91_MCI_BLKR_BLKLEN(block_length));
325
326 /*
327 * Disable the PDC controller
328 */
329 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
330
331 if (cmdr & AT91_MCI_TRCMD_START)
332 {
333 if (cmdr & AT91_MCI_TRDIR)
334 {
335 /*
336 * Handle a read
337 */
338
339 mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
340 at91_mci_init_dma_read(mci);
341 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
342 }
343 else
344 {
345 /*
346 * Handle a write
347 */
348 length = block_length * blocks;
349 /*
350 * at91mci MCI1 rev2xx Data Write Operation and
351 * number of bytes erratum
352 */
353 if (length < 12)
354 {
355 length = 12;
356 mci->buf = rt_malloc(length);
357 if (!mci->buf)
358 {
359 rt_kprintf("rt alloc tx buffer failed\n");
360 cmd->err = -RT_ENOMEM;
361 mmcsd_req_complete(mci->host);
362 return;
363 }
364 rt_memset(mci->buf, 0, 12);
365 rt_memcpy(mci->buf, data->buf, length);
366 mmu_clean_dcache((rt_uint32_t)mci->buf, length);
367 at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf));
368 at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
369 length : length / 4);
370 }
371 else
372 {
373 mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
374 at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf));
375 at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
376 length : length / 4);
377 }
378 mci_dbg("Transmitting %d bytes\n", length);
379 ier = AT91_MCI_CMDRDY;
380 }
381 }
382 }
383
384 /*
385 * Send the command and then enable the PDC - not the other way round as
386 * the data sheet says
387 */
388
389 at91_mci_write(AT91_MCI_ARGR, cmd->arg);
390 at91_mci_write(AT91_MCI_CMDR, cmdr);
391
392 if (cmdr & AT91_MCI_TRCMD_START)
393 {
394 if (cmdr & AT91_MCI_TRDIR)
395 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
396 }
397
398 /* Enable selected interrupts */
399 at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier);
400 }
401
402 /*
403 * Process the next step in the request
404 */
at91_mci_process_next(struct at91_mci * mci)405 static void at91_mci_process_next(struct at91_mci *mci)
406 {
407 if (mci->current_status == REQ_ST_INIT)
408 {
409 mci->current_status = REQ_ST_CMD;
410 at91_mci_send_command(mci, mci->req->cmd);
411 }
412 else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop)
413 {
414 mci->current_status = REQ_ST_STOP;
415 at91_mci_send_command(mci, mci->req->stop);
416 }
417 else
418 {
419 rt_timer_stop(&mci->timer);
420 /* the mci controller hangs after some transfers,
421 * and the workaround is to reset it after each transfer.
422 */
423 at91_reset_host();
424 mmcsd_req_complete(mci->host);
425 }
426 }
427
428 /*
429 * Handle an MMC request
430 */
at91_mci_request(struct rt_mmcsd_host * host,struct rt_mmcsd_req * req)431 static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
432 {
433 rt_uint32_t timeout = RT_TICK_PER_SECOND;
434 struct at91_mci *mci = host->private_data;
435 mci->req = req;
436 mci->current_status = REQ_ST_INIT;
437
438 rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout);
439 rt_timer_start(&mci->timer);
440
441 at91_mci_process_next(mci);
442 }
443
444 /*
445 * Handle transmitted data
446 */
at91_mci_handle_transmitted(struct at91_mci * mci)447 static void at91_mci_handle_transmitted(struct at91_mci *mci)
448 {
449 struct rt_mmcsd_cmd *cmd;
450 struct rt_mmcsd_data *data;
451
452 mci_dbg("Handling the transmit\n");
453
454 /* Disable the transfer */
455 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
456
457 /* Now wait for cmd ready */
458 at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
459
460 cmd = mci->cmd;
461 if (!cmd) return;
462
463 data = cmd->data;
464 if (!data) return;
465
466 if (data->blks > 1)
467 {
468 mci_dbg("multiple write : wait for BLKE...\n");
469 at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE);
470 } else
471 at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
472 }
473
474
475 /*
476 * Handle after a dma read
477 */
at91_mci_post_dma_read(struct at91_mci * mci)478 static void at91_mci_post_dma_read(struct at91_mci *mci)
479 {
480 struct rt_mmcsd_cmd *cmd;
481 struct rt_mmcsd_data *data;
482
483 mci_dbg("post dma read\n");
484
485 cmd = mci->cmd;
486 if (!cmd)
487 {
488 mci_dbg("no command\n");
489 return;
490 }
491
492 data = cmd->data;
493 if (!data)
494 {
495 mci_dbg("no data\n");
496 return;
497 }
498
499 at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX);
500 at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
501
502 mci_dbg("post dma read done\n");
503 }
504
505 /*Handle after command sent ready*/
at91_mci_handle_cmdrdy(struct at91_mci * mci)506 static int at91_mci_handle_cmdrdy(struct at91_mci *mci)
507 {
508 if (!mci->cmd)
509 return 1;
510 else if (!mci->cmd->data)
511 {
512 if (mci->current_status == REQ_ST_STOP)
513 {
514 /*After multi block write, we must wait for NOTBUSY*/
515 at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
516 }
517 else return 1;
518 }
519 else if (mci->cmd->data->flags & DATA_DIR_WRITE)
520 {
521 /*After sendding multi-block-write command, start DMA transfer*/
522 at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
523 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
524 }
525
526 /* command not completed, have to wait */
527 return 0;
528 }
529
530 /*
531 * Handle a command that has been completed
532 */
at91_mci_completed_command(struct at91_mci * mci,rt_uint32_t status)533 static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status)
534 {
535 struct rt_mmcsd_cmd *cmd = mci->cmd;
536 struct rt_mmcsd_data *data = cmd->data;
537
538 at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
539
540 cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
541 cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
542 cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
543 cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
544
545 if (mci->buf)
546 {
547 //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks);
548 rt_free(mci->buf);
549 mci->buf = RT_NULL;
550 }
551
552 mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n",
553 status, at91_mci_read(AT91_MCI_SR),
554 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
555
556 if (status & AT91_MCI_ERRORS)
557 {
558 if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4)))
559 {
560 cmd->err = 0;
561 }
562 else
563 {
564 if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE))
565 {
566 if (data)
567 {
568 if (status & AT91_MCI_DTOE)
569 data->err = -RT_ETIMEOUT;
570 else if (status & AT91_MCI_DCRCE)
571 data->err = -RT_ERROR;
572 }
573 }
574 else
575 {
576 if (status & AT91_MCI_RTOE)
577 cmd->err = -RT_ETIMEOUT;
578 else if (status & AT91_MCI_RCRCE)
579 cmd->err = -RT_ERROR;
580 else
581 cmd->err = -RT_ERROR;
582 }
583
584 rt_kprintf("error detected and set to %d/%d (cmd = %d)\n",
585 cmd->err, data ? data->err : 0,
586 cmd->cmd_code);
587 }
588 }
589 else
590 cmd->err = 0;
591
592 at91_mci_process_next(mci);
593 }
594
595 /*
596 * Handle an interrupt
597 */
at91_mci_irq(int irq,void * param)598 static void at91_mci_irq(int irq, void *param)
599 {
600 struct at91_mci *mci = (struct at91_mci *)param;
601 rt_int32_t completed = 0;
602 rt_uint32_t int_status, int_mask;
603
604 int_status = at91_mci_read(AT91_MCI_SR);
605 int_mask = at91_mci_read(AT91_MCI_IMR);
606
607 mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
608 int_status & int_mask);
609
610 int_status = int_status & int_mask;
611
612 if (int_status & AT91_MCI_ERRORS)
613 {
614 completed = 1;
615
616 if (int_status & AT91_MCI_UNRE)
617 mci_dbg("MMC: Underrun error\n");
618 if (int_status & AT91_MCI_OVRE)
619 mci_dbg("MMC: Overrun error\n");
620 if (int_status & AT91_MCI_DTOE)
621 mci_dbg("MMC: Data timeout\n");
622 if (int_status & AT91_MCI_DCRCE)
623 mci_dbg("MMC: CRC error in data\n");
624 if (int_status & AT91_MCI_RTOE)
625 mci_dbg("MMC: Response timeout\n");
626 if (int_status & AT91_MCI_RENDE)
627 mci_dbg("MMC: Response end bit error\n");
628 if (int_status & AT91_MCI_RCRCE)
629 mci_dbg("MMC: Response CRC error\n");
630 if (int_status & AT91_MCI_RDIRE)
631 mci_dbg("MMC: Response direction error\n");
632 if (int_status & AT91_MCI_RINDE)
633 mci_dbg("MMC: Response index error\n");
634 }
635 else
636 {
637 /* Only continue processing if no errors */
638
639 if (int_status & AT91_MCI_TXBUFE)
640 {
641 mci_dbg("TX buffer empty\n");
642 at91_mci_handle_transmitted(mci);
643 }
644
645 if (int_status & AT91_MCI_ENDRX)
646 {
647 mci_dbg("ENDRX\n");
648 at91_mci_post_dma_read(mci);
649 }
650
651 if (int_status & AT91_MCI_RXBUFF)
652 {
653 mci_dbg("RX buffer full\n");
654 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
655 at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
656 completed = 1;
657 }
658
659 if (int_status & AT91_MCI_ENDTX)
660 mci_dbg("Transmit has ended\n");
661
662 if (int_status & AT91_MCI_NOTBUSY)
663 {
664 mci_dbg("Card is ready\n");
665 //at91_mci_update_bytes_xfered(host);
666 completed = 1;
667 }
668
669 if (int_status & AT91_MCI_DTIP)
670 mci_dbg("Data transfer in progress\n");
671
672 if (int_status & AT91_MCI_BLKE)
673 {
674 mci_dbg("Block transfer has ended\n");
675 if (mci->req->data && mci->req->data->blks > 1)
676 {
677 /* multi block write : complete multi write
678 * command and send stop */
679 completed = 1;
680 }
681 else
682 {
683 at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
684 }
685 }
686
687 /*if (int_status & AT91_MCI_SDIOIRQA)
688 rt_mmcsd_signal_sdio_irq(host->mmc);*/
689
690 if (int_status & AT91_MCI_SDIOIRQB)
691 sdio_irq_wakeup(mci->host);
692
693 if (int_status & AT91_MCI_TXRDY)
694 mci_dbg("Ready to transmit\n");
695
696 if (int_status & AT91_MCI_RXRDY)
697 mci_dbg("Ready to receive\n");
698
699 if (int_status & AT91_MCI_CMDRDY)
700 {
701 mci_dbg("Command ready\n");
702 completed = at91_mci_handle_cmdrdy(mci);
703 }
704 }
705
706 if (completed)
707 {
708 mci_dbg("Completed command\n");
709 at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
710 at91_mci_completed_command(mci, int_status);
711 }
712 else
713 at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
714
715 }
716
717
718 /*
719 * Set the IOCFG
720 */
at91_mci_set_iocfg(struct rt_mmcsd_host * host,struct rt_mmcsd_io_cfg * io_cfg)721 static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
722 {
723 rt_uint32_t clkdiv;
724 //struct at91_mci *mci = host->private_data;
725 rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck"));
726
727 if (io_cfg->clock == 0)
728 {
729 /* Disable the MCI controller */
730 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
731 clkdiv = 0;
732 }
733 else
734 {
735 /* Enable the MCI controller */
736 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
737
738 if ((at91_master_clock % (io_cfg->clock * 2)) == 0)
739 clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1;
740 else
741 clkdiv = (at91_master_clock / io_cfg->clock) / 2;
742
743 mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv,
744 at91_master_clock / (2 * (clkdiv + 1)));
745 }
746 if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
747 {
748 mci_dbg("MMC: Setting controller bus width to 4\n");
749 at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
750 }
751 else
752 {
753 mci_dbg("MMC: Setting controller bus width to 1\n");
754 at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
755 }
756
757 /* Set the clock divider */
758 at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
759
760 /* maybe switch power to the card */
761 switch (io_cfg->power_mode)
762 {
763 case MMCSD_POWER_OFF:
764 break;
765 case MMCSD_POWER_UP:
766 break;
767 case MMCSD_POWER_ON:
768 /*at91_mci_write(AT91_MCI_ARGR, 0);
769 at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD);
770 mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR));
771 while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
772 {
773
774 }
775 mci_dbg("at91 mci power on\n");*/
776 break;
777 default:
778 rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode);
779 break;
780 }
781
782 }
783
784
at91_mci_enable_sdio_irq(struct rt_mmcsd_host * host,rt_int32_t enable)785 static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable)
786 {
787 at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB);
788 }
789
790
791 static const struct rt_mmcsd_host_ops ops = {
792 at91_mci_request,
793 at91_mci_set_iocfg,
794 RT_NULL,
795 at91_mci_enable_sdio_irq,
796 };
797
at91_mci_detect(int irq,void * param)798 void at91_mci_detect(int irq, void *param)
799 {
800 rt_kprintf("mmcsd gpio detected\n");
801 }
802
mci_gpio_init()803 static void mci_gpio_init()
804 {
805 #ifdef USE_SLOT_B
806 at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
807 at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8));
808 at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
809 at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8));
810 at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8));
811
812 at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7));
813 at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7));
814 at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7));
815 at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7));
816 #else
817 at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11));
818 at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
819 at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
820 #endif
821 }
822
at91_mci_init(void)823 int at91_mci_init(void)
824 {
825 struct rt_mmcsd_host *host;
826 struct at91_mci *mci;
827
828 host = mmcsd_alloc_host();
829 if (!host)
830 {
831 return -RT_ERROR;
832 }
833
834 mci = rt_malloc(sizeof(struct at91_mci));
835 if (!mci)
836 {
837 rt_kprintf("alloc mci failed\n");
838 goto err;
839 }
840
841 rt_memset(mci, 0, sizeof(struct at91_mci));
842
843 host->ops = &ops;
844 host->freq_min = 375000;
845 host->freq_max = 25000000;
846 host->valid_ocr = VDD_32_33 | VDD_33_34;
847 host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
848 MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
849 host->max_seg_size = 65535;
850 host->max_dma_segs = 2;
851 host->max_blk_size = 512;
852 host->max_blk_count = 4096;
853
854 mci->host = host;
855
856 mci_gpio_init();
857 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock
858
859 at91_mci_disable();
860 at91_mci_enable();
861
862 /* instal interrupt */
863 rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq,
864 (void *)mci, "MMC");
865 rt_hw_interrupt_umask(AT91SAM9260_ID_MCI);
866 rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7),
867 at91_mci_detect, RT_NULL, "MMC_DETECT");
868 rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7));
869
870 rt_timer_init(&mci->timer, "mci_timer",
871 at91_timeout_timer,
872 mci,
873 RT_TICK_PER_SECOND,
874 RT_TIMER_FLAG_PERIODIC);
875
876 //rt_timer_start(&mci->timer);
877
878 //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
879
880 host->private_data = mci;
881
882 mmcsd_change(host);
883
884 return 0;
885
886 err:
887 mmcsd_free_host(host);
888
889 return -RT_ENOMEM;
890 }
891
892 INIT_DEVICE_EXPORT(at91_mci_init);
893
894 #include "finsh.h"
895 FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init);
896
mci_dump(void)897 void mci_dump(void)
898 {
899 rt_uint32_t i;
900
901 rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR));
902 rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR));
903 rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR));
904
905 for (i = 0; i <= 0x4c; i += 4) {
906 rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i));
907 }
908 }
909
910 FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci);
911