1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-06-09 weety first version 9 */ 10 11 #ifndef __AT91_MCI_H__ 12 #define __AT91_MCI_H__ 13 14 #define AT91_MCI_CR 0x00 /* Control Register */ 15 #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ 16 #define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ 17 #define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ 18 #define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ 19 #define AT91_MCI_SWRST (1 << 7) /* Software Reset */ 20 21 #define AT91_MCI_MR 0x04 /* Mode Register */ 22 #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ 23 #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ 24 #define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ 25 #define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ 26 #define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ 27 #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ 28 #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ 29 #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ 30 31 #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ 32 #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ 33 #define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ 34 #define AT91_MCI_DTOMUL_1 (0 << 4) 35 #define AT91_MCI_DTOMUL_16 (1 << 4) 36 #define AT91_MCI_DTOMUL_128 (2 << 4) 37 #define AT91_MCI_DTOMUL_256 (3 << 4) 38 #define AT91_MCI_DTOMUL_1K (4 << 4) 39 #define AT91_MCI_DTOMUL_4K (5 << 4) 40 #define AT91_MCI_DTOMUL_64K (6 << 4) 41 #define AT91_MCI_DTOMUL_1M (7 << 4) 42 43 #define AT91_MCI_SDCR 0x0c /* SD Card Register */ 44 #define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ 45 #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ 46 47 #define AT91_MCI_ARGR 0x10 /* Argument Register */ 48 49 #define AT91_MCI_CMDR 0x14 /* Command Register */ 50 #define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ 51 #define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ 52 #define AT91_MCI_RSPTYP_NONE (0 << 6) 53 #define AT91_MCI_RSPTYP_48 (1 << 6) 54 #define AT91_MCI_RSPTYP_136 (2 << 6) 55 #define AT91_MCI_SPCMD (7 << 8) /* Special Command */ 56 #define AT91_MCI_SPCMD_NONE (0 << 8) 57 #define AT91_MCI_SPCMD_INIT (1 << 8) 58 #define AT91_MCI_SPCMD_SYNC (2 << 8) 59 #define AT91_MCI_SPCMD_ICMD (4 << 8) 60 #define AT91_MCI_SPCMD_IRESP (5 << 8) 61 #define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ 62 #define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ 63 #define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ 64 #define AT91_MCI_TRCMD_NONE (0 << 16) 65 #define AT91_MCI_TRCMD_START (1 << 16) 66 #define AT91_MCI_TRCMD_STOP (2 << 16) 67 #define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ 68 #define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ 69 #define AT91_MCI_TRTYP_BLOCK (0 << 19) 70 #define AT91_MCI_TRTYP_MULTIPLE (1 << 19) 71 #define AT91_MCI_TRTYP_STREAM (2 << 19) 72 73 #define AT91_MCI_BLKR 0x18 /* Block Register */ 74 #define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ 75 #define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ 76 77 #define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ 78 #define AT91_MCR_RDR 0x30 /* Receive Data Register */ 79 #define AT91_MCR_TDR 0x34 /* Transmit Data Register */ 80 81 #define AT91_MCI_SR 0x40 /* Status Register */ 82 #define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ 83 #define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ 84 #define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ 85 #define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ 86 #define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ 87 #define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ 88 #define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ 89 #define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ 90 #define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ 91 #define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ 92 #define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ 93 #define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ 94 #define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ 95 #define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ 96 #define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ 97 #define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ 98 #define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ 99 #define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ 100 #define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ 101 #define AT91_MCI_OVRE (1U << 30) /* Overrun */ 102 #define AT91_MCI_UNRE (1U << 31) /* Underrun */ 103 104 #define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ 105 #define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ 106 #define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ 107 108 extern int at91_mci_init(void); 109 110 #endif 111