1 /* 2 * Copyright (c) 2006-2022, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-01-08 brightsally first version 9 */ 10 11 #ifndef _ATMEL_NAND_H_ 12 #define _ATMEL_NAND_H_ 13 14 15 /* NAND flash */ 16 #define DATA_PART_ADDR 0x900000 /*nand0=0-9MB;nand1=9MB-END*/ 17 18 #define AT91C_BASE_CCFG 0xffffef14 19 #define CCFG_EBICSA 0x08 /* EBI Chip Select Assignement Register */ 20 #define AT91C_EBI_CS3A_SM (0x1UL << 3) 21 #define AT91C_BASE_SMC 0xffffec00 22 #define AT91C_BASE_PMC 0xfffffc00 23 #define SMC_SETUP3 0x30 /* Setup Register for CS 3 */ 24 #define SMC_PULSE3 0x34 /* Pulse Register for CS 3 */ 25 #define SMC_CYCLE3 0x38 /* Cycle Register for CS 3 */ 26 #define SMC_CTRL3 0x3C /* Control Register for CS 3 */ 27 28 #define AT91C_SMC_NWESETUP_(x) ((x) << 0) 29 #define AT91C_SMC_NCS_WRSETUP_(x) ((x) << 8) 30 #define AT91C_SMC_NRDSETUP_(x) ((x) << 16) 31 #define AT91C_SMC_NCS_RDSETUP_(x) ((x) << 24) 32 #define AT91C_SMC_NWEPULSE_(x) ((x) << 0) 33 #define AT91C_SMC_NCS_WRPULSE_(x) ((x) << 8) 34 #define AT91C_SMC_NRDPULSE_(x) ((x) << 16) 35 #define AT91C_SMC_NCS_RDPULSE_(x) ((x) << 24) 36 37 #define AT91C_SMC_NWECYCLE_(x) ((x) << 0) 38 #define AT91C_SMC_NRDCYCLE_(x) ((x) << 16) 39 40 #define AT91C_SMC_READMODE (0x1UL << 0) 41 #define AT91C_SMC_WRITEMODE (0x1UL << 1) 42 #define AT91C_SMC_NWAITM (0x3UL << 4) 43 #define AT91C_SMC_DBW_WIDTH_BITS_8 (0x0UL << 12) 44 #define AT91C_SMC_DBW_WIDTH_BITS_16 (0x1UL << 12) 45 #define AT91C_SMC_DBW_WIDTH_BITS_32 (0x2UL << 12) 46 #define AT91C_SMC_TDF (0xFUL << 16) 47 #define AT91_SMC_TDF_(x) ((x) << 16) 48 49 #define CMD_STATUS 0x70 50 #define STATUS_READY (0x01 << 6) /* Status code for Ready */ 51 #define STATUS_ERROR (0x01 << 0) /* Status code for Error */ 52 53 /* Nand flash commands */ 54 #define CMD_READID 0x90 55 #define CMD_READ_1 0x00 56 #define CMD_READ_2 0x30 57 58 #define CMD_READ_A0 0x00 59 #define CMD_READ_A1 0x01 60 #define CMD_READ_C 0x50 61 62 #define CMD_WRITE_A 0x00 63 #define CMD_WRITE_C 0x50 64 65 #define CMD_WRITE_1 0x80 66 #define CMD_WRITE_2 0x10 67 68 #define CMD_ERASE_1 0x60 69 #define CMD_ERASE_2 0xD0 70 71 /* read/write/move page */ 72 #define CMD_REG 0x40400000 73 #define ADDR_REG 0x40200000 74 #define DATA_REG 0x40000000 75 76 /*Values returned by the CheckBlock() function 77 GOOD = RT_EOK=0 78 BAD = -1 79 */ 80 #define BADBLOCK -RT_ERROR //-1 81 #define GOODBLOCK RT_EOK //0 82 83 struct nand_oobfree 84 { 85 unsigned int offset; 86 unsigned int length; 87 }; 88 89 struct nand_ecclayout 90 { 91 unsigned int eccbytes; 92 unsigned int eccpos[680]; 93 unsigned int oobavail; 94 struct nand_oobfree oobfree[32]; 95 }; 96 97 struct nand_chip_id 98 { 99 unsigned short chip_id; /* Nand Chip ID */ 100 unsigned short numblocks; //0x1000=4096=4K //4K*16K=64M 101 unsigned int blocksize; //0x4000=16K //SECTOR 102 unsigned short pagesize; //0X200=512 //1 BLOCK has pages=16K/512=32 103 unsigned char oobsize; //0X10=16 104 unsigned char buswidth; 105 }; 106 static struct nand_chip_id nand_ids[] = 107 { 108 109 /* Samsung 32MB 8Bit SMALL BLOCK*/ 110 {0xec75, 0x800, 0x4000, 0x200, 0x10, 0x0}, //32M 111 {0xec35, 0x800, 0x4000, 0x200, 0x10, 0x0}, //32M 112 {0xec36, 0x1000, 0x4000, 0x200, 0x10, 0x0}, //4K*16K=64M 113 /* Samsung 128MB 8bit BIG BLOCK*/ 114 {0xeca1, 0x400, 0x20000, 0x800, 0x40, 0x0}, //128M 115 {0,} 116 }; 117 118 119 int rt_hw_mtd_nand_init(void); 120 #endif 121