1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2011-01-13 weety first version
9 */
10
11 #include <rtthread.h>
12 #include <rthw.h>
13
14 #include "board.h"
15 #include <mmu.h>
16
17 /**
18 * @addtogroup at91sam9260
19 */
20 /*@{*/
21 #if defined(__CC_ARM)
22 extern int Image$$ER_ZI$$ZI$$Limit;
23 #define HEAP_BEGIN (&Image$$ER_ZI$$ZI$$Limit)
24 #elif (defined (__GNUC__))
25 extern unsigned char __bss_end__;
26 #define HEAP_BEGIN (&__bss_end__)
27 #elif (defined (__ICCARM__))
28 #pragma section=".noinit"
29 #define HEAP_BEGIN (__section_end(".noinit"))
30 #endif
31
32 #define HEAP_END (((rt_uint32_t)HEAP_BEGIN & (0xF0 << 24)) + (32 << 20))
33
34 extern void rt_hw_interrupt_init(void);
35 extern void rt_hw_clock_init(void);
36
37 extern void rt_hw_get_clock(void);
38 extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
39 extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
40 extern void rt_dbgu_isr(void);
41
42 static struct mem_desc at91_mem_desc[] = {
43 { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */
44 { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */
45 { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */
46 { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
47 { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */
48 };
49
50
51 #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
52 #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
53
54 static rt_uint32_t pit_cycle; /* write-once */
55 static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
56
57 /**
58 * This function will handle rtos timer
59 */
rt_timer_handler(int vector,void * param)60 void rt_timer_handler(int vector, void *param)
61 {
62 #ifdef RT_USING_DBGU
63 if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1)
64 {
65 rt_dbgu_isr();
66 }
67 #endif
68 if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)
69 {
70 unsigned nr_ticks;
71
72 /* Get number of ticks performed before irq, and ack it */
73 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
74 rt_tick_increase();
75 }
76 }
77
at91sam926x_pit_reset(void)78 static void at91sam926x_pit_reset(void)
79 {
80 /* Disable timer and irqs */
81 at91_sys_write(AT91_PIT_MR, 0);
82
83 /* Clear any pending interrupts, wait for PIT to stop counting */
84 while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
85 ;
86
87 /* Start PIT but don't enable IRQ */
88 //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
89 pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
90 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
91 | AT91_PIT_PITIEN);
92 rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
93 }
94
95 /*
96 * Set up both clocksource and clockevent support.
97 */
at91sam926x_pit_init(void)98 static void at91sam926x_pit_init(void)
99 {
100 rt_uint32_t pit_rate;
101 rt_uint32_t bits;
102
103 /*
104 * Use our actual MCK to figure out how many MCK/16 ticks per
105 * 1/HZ period (instead of a compile-time constant LATCH).
106 */
107 pit_rate = clk_get_rate(clk_get("mck")) / 16;
108 rt_kprintf("pit_rate=%dHZ\n", pit_rate);
109 pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
110
111 /* Initialize and enable the timer */
112 at91sam926x_pit_reset();
113
114 }
115
116 /**
117 * This function will init pit for system ticks
118 */
rt_hw_timer_init()119 void rt_hw_timer_init()
120 {
121 at91sam926x_pit_init();
122
123 /* install interrupt handler */
124 rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler,
125 RT_NULL, "system");
126 rt_hw_interrupt_umask(AT91_ID_SYS);
127
128 }
129
at91_tc1_init()130 void at91_tc1_init()
131 {
132 at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
133 writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
134 writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
135 writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
136 writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
137 }
138
139 #define RXRDY 0x01
140 #define TXRDY (1 << 1)
141 #define BPS 115200 /* serial baudrate */
142
143 typedef struct uartport
144 {
145 volatile rt_uint32_t CR;
146 volatile rt_uint32_t MR;
147 volatile rt_uint32_t IER;
148 volatile rt_uint32_t IDR;
149 volatile rt_uint32_t IMR;
150 volatile rt_uint32_t CSR;
151 volatile rt_uint32_t RHR;
152 volatile rt_uint32_t THR;
153 volatile rt_uint32_t BRGR;
154 volatile rt_uint32_t RTOR;
155 volatile rt_uint32_t TTGR;
156 volatile rt_uint32_t reserved0[5];
157 volatile rt_uint32_t FIDI;
158 volatile rt_uint32_t NER;
159 volatile rt_uint32_t reserved1;
160 volatile rt_uint32_t IFR;
161 volatile rt_uint32_t reserved2[44];
162 volatile rt_uint32_t RPR;
163 volatile rt_uint32_t RCR;
164 volatile rt_uint32_t TPR;
165 volatile rt_uint32_t TCR;
166 volatile rt_uint32_t RNPR;
167 volatile rt_uint32_t RNCR;
168 volatile rt_uint32_t TNPR;
169 volatile rt_uint32_t TNCR;
170 volatile rt_uint32_t PTCR;
171 volatile rt_uint32_t PTSR;
172 }uartport;
173
174 #define CIDR FIDI
175 #define EXID NER
176 #define FNR reserved1
177
178 #define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU)
179
at91_usart_putc(char c)180 static void at91_usart_putc(char c)
181 {
182 while (!(DBGU->CSR & TXRDY));
183 DBGU->THR = c;
184 }
185
186 /**
187 * This function is used to display a string on console, normally, it's
188 * invoked by rt_kprintf
189 *
190 * @param str the displayed string
191 */
rt_hw_console_output(const char * str)192 void rt_hw_console_output(const char* str)
193 {
194 while (*str)
195 {
196 if (*str=='\n')
197 {
198 at91_usart_putc('\r');
199 }
200
201 at91_usart_putc(*str++);
202 }
203 }
204
rt_hw_console_init(void)205 static void rt_hw_console_init(void)
206 {
207 int div;
208 int mode = 0;
209
210 DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX |
211 AT91_US_RXDIS | AT91_US_TXDIS;
212 mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
213 AT91_US_CHMODE_NORMAL;
214 mode |= AT91_US_CHRL_8;
215 mode |= AT91_US_NBSTOP_1;
216 mode |= AT91_US_PAR_NONE;
217 DBGU->MR = mode;
218 div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
219 DBGU->BRGR = div;
220 DBGU->CR = AT91_US_RXEN | AT91_US_TXEN;
221 }
222
223
224 /**
225 * This function will init at91sam9260 board
226 */
rt_hw_board_init()227 void rt_hw_board_init()
228 {
229 /* initialize the system clock */
230 rt_hw_clock_init();
231
232 /* initialize console */
233 rt_hw_console_init();
234
235 /* initialize mmu */
236 rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
237
238 /* initialize hardware interrupt */
239 rt_hw_interrupt_init();
240
241 /* initialize early device */
242 #ifdef RT_USING_COMPONENTS_INIT
243 rt_components_board_init();
244 #endif
245
246 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
247 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
248 #endif
249
250 /* initialize timer0 */
251 rt_hw_timer_init();
252
253 /* initialize board */
254 #ifdef RT_USING_HEAP
255 rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
256 #endif
257
258 }
259
260 /*@}*/
261