1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2011-03-18 weety first version
9 */
10
11 #include <rtthread.h>
12 #include <netif/ethernetif.h>
13 #include "lwipopts.h"
14 #include <at91sam926x.h>
15 #include "macb.h"
16
17 #define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
18
19 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
20 extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
21
22 /* Cache macros - Packet buffers would be from pbuf pool which is cached */
23 #define EMAC_VIRT_NOCACHE(addr) (addr)
24 #define EMAC_CACHE_INVALIDATE(addr, size) \
25 mmu_invalidate_dcache((rt_uint32_t)addr, size)
26 #define EMAC_CACHE_WRITEBACK(addr, size) \
27 mmu_clean_dcache((rt_uint32_t)addr, size)
28 #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
29 mmu_clean_invalidated_dcache((rt_uint32_t)addr, size)
30
31 /* EMAC has BD's in cached memory - so need cache functions */
32 #define BD_CACHE_INVALIDATE(addr, size)
33 #define BD_CACHE_WRITEBACK(addr, size)
34 #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
35
36 /* EMAC internal utility function */
emac_virt_to_phys(unsigned long addr)37 rt_inline unsigned long emac_virt_to_phys(unsigned long addr)
38 {
39 return addr;
40 }
41
42
43 #define AT91SAM9260_SRAM0_VIRT_BASE (0x90000000)
44
45 #define MACB_TX_SRAM
46
47 #if defined(MACB_TX_SRAM)
48 #define MACB_TX_RING_SIZE 2
49 #define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
50 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE)
51 #else
52 #define MACB_TX_RING_SIZE 16
53 #define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
54 #endif
55
56 #define MACB_RX_BUFFER_SIZE (4096*4)
57 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
58
59 #define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE)
60
61 #define TX_RING_GAP(macb) \
62 (MACB_TX_RING_SIZE - (macb)->tx_pending)
63
64 #define TX_BUFFS_AVAIL(macb) \
65 (((macb)->tx_tail <= (macb)->tx_head) ? \
66 (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \
67 (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb))
68
69 #define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1))
70
71 #define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1))
72
73 /* minimum number of free TX descriptors before waking up TX process */
74 #define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4)
75
76 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
77 | MACB_BIT(ISR_ROVR))
78
79 #define MACB_TX_TIMEOUT 1000
80 #define MACB_AUTONEG_TIMEOUT 5000000
81 #define MACB_LINK_TIMEOUT 500000
82
83 #define CONFIG_RMII
84
85 struct macb_dma_desc {
86 rt_uint32_t addr;
87 rt_uint32_t ctrl;
88 };
89
90 #define RXADDR_USED 0x00000001
91 #define RXADDR_WRAP 0x00000002
92
93 #define RXBUF_FRMLEN_MASK 0x00000fff
94 #define RXBUF_FRAME_START 0x00004000
95 #define RXBUF_FRAME_END 0x00008000
96 #define RXBUF_TYPEID_MATCH 0x00400000
97 #define RXBUF_ADDR4_MATCH 0x00800000
98 #define RXBUF_ADDR3_MATCH 0x01000000
99 #define RXBUF_ADDR2_MATCH 0x02000000
100 #define RXBUF_ADDR1_MATCH 0x04000000
101 #define RXBUF_BROADCAST 0x80000000
102
103 #define TXBUF_FRMLEN_MASK 0x000007ff
104 #define TXBUF_FRAME_END 0x00008000
105 #define TXBUF_NOCRC 0x00010000
106 #define TXBUF_EXHAUSTED 0x08000000
107 #define TXBUF_UNDERRUN 0x10000000
108 #define TXBUF_MAXRETRY 0x20000000
109 #define TXBUF_WRAP 0x40000000
110 #define TXBUF_USED 0x80000000
111
112 /* Duplex, half or full. */
113 #define DUPLEX_HALF 0x00
114 #define DUPLEX_FULL 0x01
115
116 #define MAX_ADDR_LEN 6
117 struct rt_macb_eth
118 {
119 /* inherit from ethernet device */
120 struct eth_device parent;
121
122 unsigned int regs;
123
124 unsigned int rx_tail;
125 unsigned int tx_head;
126 unsigned int tx_tail;
127 unsigned int rx_pending;
128 unsigned int tx_pending;
129
130 void *rx_buffer;
131 void *tx_buffer;
132 struct macb_dma_desc *rx_ring;
133 struct macb_dma_desc *tx_ring;
134
135 unsigned long rx_buffer_dma;
136 unsigned long tx_buffer_dma;
137 unsigned long rx_ring_dma;
138 unsigned long tx_ring_dma;
139
140 unsigned int tx_stop;
141
142 /* interface address info. */
143 rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
144 unsigned short phy_addr;
145
146 struct rt_semaphore mdio_bus_lock;
147 struct rt_semaphore tx_lock;
148 struct rt_semaphore rx_lock;
149 struct rt_semaphore tx_ack;
150 rt_uint32_t speed;
151 rt_uint32_t duplex;
152 rt_uint32_t link;
153 struct rt_timer timer;
154 };
155 static struct rt_macb_eth macb_device;
156
157 static void macb_tx(struct rt_macb_eth *macb);
158
udelay(rt_uint32_t us)159 static void udelay(rt_uint32_t us)
160 {
161 rt_uint32_t len;
162 for (;us > 0; us --)
163 for (len = 0; len < 10; len++ );
164 }
165
rt_macb_isr(int irq,void * param)166 static void rt_macb_isr(int irq, void *param)
167 {
168 struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
169 rt_device_t dev = &(macb->parent.parent);
170 rt_uint32_t status, rsr, tsr;
171
172 status = macb_readl(macb, ISR);
173
174 while (status) {
175
176 if (status & MACB_RX_INT_FLAGS)
177 {
178 rsr = macb_readl(macb, RSR);
179 macb_writel(macb, RSR, rsr);
180 /* a frame has been received */
181 eth_device_ready(&(macb_device.parent));
182
183 }
184
185 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
186 MACB_BIT(ISR_RLE)))
187 {
188 macb_tx(macb);
189 }
190
191 /*
192 * Link change detection isn't possible with RMII, so we'll
193 * add that if/when we get our hands on a full-blown MII PHY.
194 */
195
196 if (status & MACB_BIT(HRESP))
197 {
198 /*
199 * TODO: Reset the hardware, and maybe move the printk
200 * to a lower-priority context as well (work queue?)
201 */
202 rt_kprintf("%s: DMA bus error: HRESP not OK\n",
203 dev->parent.name);
204 }
205
206 status = macb_readl(macb, ISR);
207 }
208
209
210 }
211
macb_mdio_write(struct rt_macb_eth * macb,rt_uint8_t reg,rt_uint16_t value)212 static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value)
213 {
214 unsigned long netctl;
215 unsigned long netstat;
216 unsigned long frame;
217
218 rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
219 netctl = macb_readl(macb, NCR);
220 netctl |= MACB_BIT(MPE);
221 macb_writel(macb, NCR, netctl);
222
223 frame = (MACB_BF(SOF, 1)
224 | MACB_BF(RW, 1)
225 | MACB_BF(PHYA, macb->phy_addr)
226 | MACB_BF(REGA, reg)
227 | MACB_BF(CODE, 2)
228 | MACB_BF(DATA, value));
229 macb_writel(macb, MAN, frame);
230
231 do {
232 netstat = macb_readl(macb, NSR);
233 } while (!(netstat & MACB_BIT(IDLE)));
234
235 netctl = macb_readl(macb, NCR);
236 netctl &= ~MACB_BIT(MPE);
237 macb_writel(macb, NCR, netctl);
238 rt_sem_release(&macb->mdio_bus_lock);
239 }
240
macb_mdio_read(struct rt_macb_eth * macb,rt_uint8_t reg)241 static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg)
242 {
243 unsigned long netctl;
244 unsigned long netstat;
245 unsigned long frame;
246
247 rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
248 netctl = macb_readl(macb, NCR);
249 netctl |= MACB_BIT(MPE);
250 macb_writel(macb, NCR, netctl);
251
252 frame = (MACB_BF(SOF, 1)
253 | MACB_BF(RW, 2)
254 | MACB_BF(PHYA, macb->phy_addr)
255 | MACB_BF(REGA, reg)
256 | MACB_BF(CODE, 2));
257 macb_writel(macb, MAN, frame);
258
259 do {
260 netstat = macb_readl(macb, NSR);
261 } while (!(netstat & MACB_BIT(IDLE)));
262
263 frame = macb_readl(macb, MAN);
264
265 netctl = macb_readl(macb, NCR);
266 netctl &= ~MACB_BIT(MPE);
267 macb_writel(macb, NCR, netctl);
268 rt_sem_release(&macb->mdio_bus_lock);
269
270 return MACB_BFEXT(DATA, frame);
271 }
272
macb_phy_reset(rt_device_t dev)273 static void macb_phy_reset(rt_device_t dev)
274 {
275 int i;
276 rt_uint16_t status, adv;
277 struct rt_macb_eth *macb = dev->user_data;;
278
279 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
280 macb_mdio_write(macb, MII_ADVERTISE, adv);
281 rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name);
282 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
283 | BMCR_ANRESTART));
284
285 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++)
286 {
287 status = macb_mdio_read(macb, MII_BMSR);
288 if (status & BMSR_ANEGCOMPLETE)
289 break;
290 udelay(100);
291 }
292
293 if (status & BMSR_ANEGCOMPLETE)
294 rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name);
295 else
296 rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n",
297 dev->parent.name, status);
298 }
299
300
macb_phy_init(rt_device_t dev)301 static int macb_phy_init(rt_device_t dev)
302 {
303 struct rt_macb_eth *macb = dev->user_data;
304 rt_uint32_t ncfgr;
305 rt_uint16_t phy_id, status, adv, lpa;
306 int media, speed, duplex;
307 int i;
308
309 /* Check if the PHY is up to snuff... */
310 phy_id = macb_mdio_read(macb, MII_PHYSID1);
311 if (phy_id == 0xffff)
312 {
313 rt_kprintf("%s: No PHY present\n", dev->parent.name);
314 return 0;
315 }
316
317 status = macb_mdio_read(macb, MII_BMSR);
318 if (!(status & BMSR_LSTATUS))
319 {
320 /* Try to re-negotiate if we don't have link already. */
321 macb_phy_reset(dev);
322
323 for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++)
324 {
325 status = macb_mdio_read(macb, MII_BMSR);
326 if (status & BMSR_LSTATUS)
327 break;
328 udelay(100);
329 }
330 }
331
332 if (!(status & BMSR_LSTATUS))
333 {
334 rt_kprintf("%s: link down (status: 0x%04x)\n",
335 dev->parent.name, status);
336 return 0;
337 }
338 else
339 {
340 adv = macb_mdio_read(macb, MII_ADVERTISE);
341 lpa = macb_mdio_read(macb, MII_LPA);
342 media = mii_nway_result(lpa & adv);
343 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
344 ? 1 : 0);
345 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
346 rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
347 dev->parent.name,
348 speed ? "100" : "10",
349 duplex ? "full" : "half",
350 lpa);
351
352 ncfgr = macb_readl(macb, NCFGR);
353 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
354 if (speed)
355 ncfgr |= MACB_BIT(SPD);
356 if (duplex)
357 ncfgr |= MACB_BIT(FD);
358 macb_writel(macb, NCFGR, ncfgr);
359 return 1;
360 }
361 }
362
macb_update_link(void * param)363 void macb_update_link(void *param)
364 {
365 struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
366 rt_device_t dev = &macb->parent.parent;
367 int status, status_change = 0;
368 rt_uint32_t link;
369 rt_uint32_t media;
370 rt_uint16_t adv, lpa;
371
372 /* Do a fake read */
373 status = macb_mdio_read(macb, MII_BMSR);
374 if (status < 0)
375 return;
376
377 /* Read link and autonegotiation status */
378 status = macb_mdio_read(macb, MII_BMSR);
379 if (status < 0)
380 return;
381
382 if ((status & BMSR_LSTATUS) == 0)
383 link = 0;
384 else
385 link = 1;
386
387 if (link != macb->link)
388 {
389 macb->link = link;
390 status_change = 1;
391 }
392
393 if (status_change)
394 {
395 if (macb->link)
396 {
397 adv = macb_mdio_read(macb, MII_ADVERTISE);
398 lpa = macb_mdio_read(macb, MII_LPA);
399 media = mii_nway_result(lpa & adv);
400 macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
401 ? 100 : 10);
402 macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0;
403 rt_kprintf("%s: link up (%dMbps/%s-duplex)\n",
404 dev->parent.name, macb->speed,
405 DUPLEX_FULL == macb->duplex ? "Full":"Half");
406 eth_device_linkchange(&macb->parent, RT_TRUE);
407 }
408 else
409 {
410 rt_kprintf("%s: link down\n", dev->parent.name);
411 eth_device_linkchange(&macb->parent, RT_FALSE);
412 }
413
414 }
415
416 }
417
418 /* RT-Thread Device Interface */
419 /* initialize the interface */
420
rt_macb_init(rt_device_t dev)421 static rt_err_t rt_macb_init(rt_device_t dev)
422 {
423 struct rt_macb_eth *macb = dev->user_data;
424 unsigned long paddr;
425 rt_uint32_t hwaddr_bottom;
426 rt_uint16_t hwaddr_top;
427 int i;
428
429 /*
430 * macb_halt should have been called at some point before now,
431 * so we'll assume the controller is idle.
432 */
433
434 /* initialize DMA descriptors */
435 paddr = macb->rx_buffer_dma;
436 for (i = 0; i < MACB_RX_RING_SIZE; i++)
437 {
438 if (i == (MACB_RX_RING_SIZE - 1))
439 paddr |= RXADDR_WRAP;
440 macb->rx_ring[i].addr = paddr;
441 macb->rx_ring[i].ctrl = 0;
442 paddr += 128;
443 }
444 paddr = macb->tx_buffer_dma;
445 for (i = 0; i < MACB_TX_RING_SIZE; i++)
446 {
447 macb->tx_ring[i].addr = paddr;
448 if (i == (MACB_TX_RING_SIZE - 1))
449 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
450 else
451 macb->tx_ring[i].ctrl = TXBUF_USED;
452 paddr += 1536;
453 }
454 macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
455
456 BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
457 BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
458 macb_writel(macb, RBQP, macb->rx_ring_dma);
459 macb_writel(macb, TBQP, macb->tx_ring_dma);
460
461 /* set hardware address */
462 hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr));
463 macb_writel(macb, SA1B, hwaddr_bottom);
464 hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4)));
465 macb_writel(macb, SA1T, hwaddr_top);
466
467
468 /* choose RMII or MII mode. This depends on the board */
469 #ifdef CONFIG_RMII
470 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
471 #else
472 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
473 #endif /* CONFIG_RMII */
474
475 if (!macb_phy_init(dev))
476 return -RT_ERROR;
477
478 /* Enable TX and RX */
479 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE));
480
481 /* Enable interrupts */
482 macb_writel(macb, IER, (MACB_BIT(RCOMP)
483 | MACB_BIT(RXUBR)
484 | MACB_BIT(ISR_TUND)
485 | MACB_BIT(ISR_RLE)
486 | MACB_BIT(TXERR)
487 | MACB_BIT(TCOMP)
488 | MACB_BIT(ISR_ROVR)
489 | MACB_BIT(HRESP)));
490
491 /* instal interrupt */
492 rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr,
493 (void *)macb, "emac");
494 rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC);
495
496 rt_timer_init(&macb->timer, "link_timer",
497 macb_update_link,
498 (void *)macb,
499 RT_TICK_PER_SECOND,
500 RT_TIMER_FLAG_PERIODIC);
501
502 rt_timer_start(&macb->timer);
503
504 return RT_EOK;
505 }
506
rt_macb_open(rt_device_t dev,rt_uint16_t oflag)507 static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag)
508 {
509 return RT_EOK;
510 }
511
rt_macb_close(rt_device_t dev)512 static rt_err_t rt_macb_close(rt_device_t dev)
513 {
514 return RT_EOK;
515 }
516
rt_macb_read(rt_device_t dev,rt_off_t pos,void * buffer,rt_size_t size)517 static rt_ssize_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
518 {
519 rt_set_errno(-RT_ENOSYS);
520 return 0;
521 }
522
rt_macb_write(rt_device_t dev,rt_off_t pos,const void * buffer,rt_size_t size)523 static rt_ssize_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
524 {
525 rt_set_errno(-RT_ENOSYS);
526 return 0;
527 }
528
rt_macb_control(rt_device_t dev,int cmd,void * args)529 static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args)
530 {
531 switch(cmd)
532 {
533 case NIOCTL_GADDR:
534 /* get mac address */
535 if(args) rt_memcpy(args, macb_device.dev_addr, 6);
536 else return -RT_ERROR;
537 break;
538
539 default :
540 break;
541 }
542
543 return RT_EOK;
544 }
545
macb_tx(struct rt_macb_eth * macb)546 static void macb_tx(struct rt_macb_eth *macb)
547 {
548 unsigned int tail;
549 unsigned int head;
550 rt_uint32_t status;
551
552 status = macb_readl(macb, TSR);
553 macb_writel(macb, TSR, status);
554
555 /*rt_kprintf("macb_tx status = %02lx\n",
556 (unsigned long)status);*/
557
558 if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE)))
559 {
560 int i;
561 rt_kprintf("%s: TX %s, resetting buffers\n",
562 macb->parent.parent.parent.name, status & MACB_BIT(UND) ?
563 "underrun" : "retry limit exceeded");
564
565 /* Transfer ongoing, disable transmitter, to avoid confusion */
566 if (status & MACB_BIT(TGO))
567 macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
568
569 head = macb->tx_head;
570
571 /*Mark all the buffer as used to avoid sending a lost buffer*/
572 for (i = 0; i < MACB_TX_RING_SIZE; i++)
573 macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
574
575 /* free transmit buffer in upper layer*/
576
577 macb->tx_head = macb->tx_tail = 0;
578
579 /* Enable the transmitter again */
580 if (status & MACB_BIT(TGO))
581 macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE));
582 }
583
584 if (!(status & MACB_BIT(COMP)))
585 /*
586 * This may happen when a buffer becomes complete
587 * between reading the ISR and scanning the
588 * descriptors. Nothing to worry about.
589 */
590 return;
591
592 head = macb->tx_head;
593 for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail))
594 {
595 rt_uint32_t bufstat;
596
597 bufstat = macb->tx_ring[tail].ctrl;
598
599 if (!(bufstat & MACB_BIT(TX_USED)))
600 break;
601 }
602
603 macb->tx_tail = tail;
604 if ((macb->tx_stop == 1) &&
605 TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH)
606 rt_sem_release(&macb->tx_ack);
607 }
608
609
610 /* ethernet device interface */
611 /* transmit packet. */
rt_macb_tx(rt_device_t dev,struct pbuf * p)612 rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p)
613 {
614 unsigned long ctrl;
615 struct pbuf* q;
616 rt_uint8_t* bufptr;
617 rt_uint32_t mapping;
618 struct rt_macb_eth *macb = dev->user_data;
619 unsigned int tx_head = macb->tx_head;
620
621 rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER);
622 if (TX_BUFFS_AVAIL(macb) < 1)
623 {
624 rt_sem_release(&macb->tx_lock);
625 rt_kprintf("Tx Ring full!\n");
626 rt_kprintf("tx_head = %u, tx_tail = %u\n",
627 macb->tx_head, macb->tx_tail);
628 return -RT_ERROR;
629 }
630
631 macb->tx_stop = 0;
632
633 ctrl = p->tot_len & TXBUF_FRMLEN_MASK;
634 ctrl |= TXBUF_FRAME_END;
635 if (tx_head == (MACB_TX_RING_SIZE - 1))
636 {
637 ctrl |= TXBUF_WRAP;
638 }
639 #if defined(MACB_TX_SRAM)
640 bufptr = macb->tx_buffer + tx_head * 1536;
641 #else
642 mapping = (unsigned long)macb->tx_buffer + tx_head * 1536;
643 bufptr = (rt_uint8_t *)mapping;
644 #endif
645
646 for (q = p; q != NULL; q = q->next)
647 {
648 memcpy(bufptr, q->payload, q->len);
649 bufptr += q->len;
650 }
651 #if !defined(MACB_TX_SRAM)
652 EMAC_CACHE_WRITEBACK(mapping, p->tot_len);
653 #endif
654 macb->tx_ring[tx_head].ctrl = ctrl;
655 BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc));
656 tx_head = NEXT_TX(tx_head);
657 macb->tx_head = tx_head;
658 macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
659 macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
660
661 if (TX_BUFFS_AVAIL(macb) < 1)
662 {
663 macb->tx_stop = 1;
664 rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER);
665 }
666 rt_sem_release(&macb->tx_lock);
667
668 return RT_EOK;
669 }
670
reclaim_rx_buffers(struct rt_macb_eth * macb,unsigned int new_tail)671 static void reclaim_rx_buffers(struct rt_macb_eth *macb,
672 unsigned int new_tail)
673 {
674 unsigned int i;
675
676 i = macb->rx_tail;
677 while (i > new_tail)
678 {
679 macb->rx_ring[i].addr &= ~RXADDR_USED;
680 i++;
681 if (i > MACB_RX_RING_SIZE)
682 i = 0;
683 }
684
685 while (i < new_tail)
686 {
687 macb->rx_ring[i].addr &= ~RXADDR_USED;
688 i++;
689 }
690
691 macb->rx_tail = new_tail;
692 }
693
694 /* reception packet. */
rt_macb_rx(rt_device_t dev)695 struct pbuf *rt_macb_rx(rt_device_t dev)
696 {
697 struct rt_macb_eth *macb = dev->user_data;
698 struct pbuf* p = RT_NULL;
699 rt_uint32_t len;
700 unsigned int rx_tail = macb->rx_tail;
701 void *buffer;
702 int wrapped = 0;
703 rt_uint32_t status;
704
705 rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER);
706 for (;;)
707 {
708 if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
709 break;
710
711 status = macb->rx_ring[rx_tail].ctrl;
712 if (status & RXBUF_FRAME_START)
713 {
714 if (rx_tail != macb->rx_tail)
715 reclaim_rx_buffers(macb, rx_tail);
716 wrapped = 0;
717 }
718
719 if (status & RXBUF_FRAME_END)
720 {
721 buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail);
722 len = status & RXBUF_FRMLEN_MASK;
723 p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
724 if (!p)
725 {
726 rt_kprintf("alloc pbuf failed\n");
727 break;
728 }
729 if (wrapped)
730 {
731 unsigned int headlen, taillen;
732
733 headlen = 128 * (MACB_RX_RING_SIZE
734 - macb->rx_tail);
735 taillen = len - headlen;
736 EMAC_CACHE_INVALIDATE(buffer, headlen);
737 EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen);
738 memcpy((void *)p->payload, buffer, headlen);
739 memcpy((void *)((unsigned int)p->payload + headlen),
740 macb->rx_buffer, taillen);
741 }
742 else
743 {
744 EMAC_CACHE_INVALIDATE(buffer, len);
745 memcpy((void *)p->payload, buffer, p->len);
746 }
747
748 if (++rx_tail >= MACB_RX_RING_SIZE)
749 rx_tail = 0;
750 reclaim_rx_buffers(macb, rx_tail);
751 break;
752 }
753 else
754 {
755 if (++rx_tail >= MACB_RX_RING_SIZE)
756 {
757 wrapped = 1;
758 rx_tail = 0;
759 }
760 }
761 }
762
763 rt_sem_release(&macb->rx_lock);
764
765 return p;
766 }
767
macb_gpio_init()768 void macb_gpio_init()
769 {
770 /* Pins used for MII and RMII */
771 at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20));
772 at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20));
773
774 #ifndef GONFIG_RMII
775 at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29));
776 at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29));
777 #endif
778 }
779
macb_initialize()780 rt_err_t macb_initialize()
781 {
782 struct rt_macb_eth *macb = &macb_device;
783 unsigned long macb_hz;
784 rt_uint32_t ncfgr;
785
786 #if defined(MACB_TX_SRAM)
787 macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE;
788 macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE;
789 macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES;
790 macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES;
791 #else
792 macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
793 if (macb->tx_ring == RT_NULL)
794 goto err1;
795 EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
796 macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring);
797 macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring);
798 macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE);
799 if (macb->tx_buffer == RT_NULL)
800 goto err2;
801 macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer);
802 #endif
803
804 macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
805 if (macb->rx_ring == RT_NULL)
806 goto err3;
807 EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
808 macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring);
809 macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring);
810 macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE);
811 if (macb->rx_buffer == RT_NULL)
812 goto err4;
813 macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer);
814
815 macb->tx_pending = DEF_TX_RING_PENDING;
816
817 macb->regs = AT91SAM9260_BASE_EMAC;
818 macb->phy_addr = 0x00;
819
820 /*
821 * Do some basic initialization so that we at least can talk
822 * to the PHY
823 */
824 macb_hz = clk_get_rate(clk_get("mck"));
825 if (macb_hz < 20000000)
826 ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
827 else if (macb_hz < 40000000)
828 ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
829 else if (macb_hz < 80000000)
830 ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
831 else
832 ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
833
834 macb_writel(macb, NCFGR, ncfgr);
835
836 macb->link = 0;
837
838 return RT_EOK;
839
840 err4:
841 rt_free(macb->rx_ring);
842 macb->rx_ring = RT_NULL;
843 err3:
844 #if !defined(MACB_TX_SRAM)
845 rt_free(macb->tx_buffer);
846 macb->tx_buffer = RT_NULL;
847 err2:
848 rt_free(macb->tx_ring);
849 macb->tx_ring = RT_NULL;
850 err1:
851 #endif
852 return -RT_ENOMEM;
853 }
854
rt_hw_macb_init(void)855 int rt_hw_macb_init(void)
856 {
857 rt_err_t ret;
858 at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock
859 macb_gpio_init();
860 rt_memset(&macb_device, 0, sizeof(macb_device));
861 ret = macb_initialize();
862 if (ret != RT_EOK)
863 {
864 rt_kprintf("AT91 EMAC initialized failed\n");
865 return -1;
866 }
867 rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO);
868 rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO);
869 rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO);
870
871 macb_device.dev_addr[0] = 0x00;
872 macb_device.dev_addr[1] = 0x60;
873 macb_device.dev_addr[2] = 0x6E;
874 macb_device.dev_addr[3] = 0x11;
875 macb_device.dev_addr[4] = 0x22;
876 macb_device.dev_addr[5] = 0x33;
877
878 macb_device.parent.parent.init = rt_macb_init;
879 macb_device.parent.parent.open = rt_macb_open;
880 macb_device.parent.parent.close = rt_macb_close;
881 macb_device.parent.parent.read = rt_macb_read;
882 macb_device.parent.parent.write = rt_macb_write;
883 macb_device.parent.parent.control = rt_macb_control;
884 macb_device.parent.parent.user_data = &macb_device;
885
886 macb_device.parent.eth_rx = rt_macb_rx;
887 macb_device.parent.eth_tx = rt_macb_tx;
888
889 rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO);
890
891 eth_device_init(&(macb_device.parent), "e0");
892
893 return 0;
894 }
895
896 INIT_DEVICE_EXPORT(rt_hw_macb_init);
897
898