1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-01-13 weety first version 9 */ 10 11 #ifndef AT91_AIC_H 12 #define AT91_AIC_H 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #define AIC_IRQS 32 19 20 #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ 21 #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ 22 #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ 23 #define AT91_AIC_SRCTYPE_LOW (0 << 5) 24 #define AT91_AIC_SRCTYPE_FALLING (1 << 5) 25 #define AT91_AIC_SRCTYPE_HIGH (2 << 5) 26 #define AT91_AIC_SRCTYPE_RISING (3 << 5) 27 28 #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ 29 #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ 30 #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ 31 #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ 32 #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ 33 34 #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ 35 #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ 36 #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ 37 #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ 38 #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ 39 40 #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ 41 #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ 42 #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ 43 #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ 44 #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ 45 #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ 46 #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ 47 #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ 48 #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ 49 50 #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ 51 #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ 52 #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ 53 54 #ifdef __cplusplus 55 } 56 #endif 57 58 #endif 59 60