1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-01-13 weety first version 9 */ 10 11 #ifndef AT91_PMC_H 12 #define AT91_PMC_H 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ 19 #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ 20 21 #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ 22 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ 23 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ 24 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 25 #define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ 26 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 27 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ 28 #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ 29 #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ 30 #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ 31 #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 32 #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ 33 #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ 34 #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ 35 #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ 36 #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ 37 38 #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ 39 #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ 40 #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ 41 42 #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ 43 #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ 44 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ 45 #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ 46 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ 47 48 #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ 49 #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 50 #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ 51 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 52 53 #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ 54 #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ 55 #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ 56 57 #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ 58 #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ 59 #define AT91_PMC_DIV (0xff << 0) /* Divider */ 60 #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ 61 #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ 62 #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ 63 #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ 64 #define AT91_PMC_USBDIV_1 (0 << 28) 65 #define AT91_PMC_USBDIV_2 (1 << 28) 66 #define AT91_PMC_USBDIV_4 (2 << 28) 67 #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ 68 69 #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ 70 #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ 71 #define AT91_PMC_CSS_SLOW (0 << 0) 72 #define AT91_PMC_CSS_MAIN (1 << 0) 73 #define AT91_PMC_CSS_PLLA (2 << 0) 74 #define AT91_PMC_CSS_PLLB (3 << 0) 75 #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ 76 #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ 77 #define AT91_PMC_PRES_1 (0 << 2) 78 #define AT91_PMC_PRES_2 (1 << 2) 79 #define AT91_PMC_PRES_4 (2 << 2) 80 #define AT91_PMC_PRES_8 (3 << 2) 81 #define AT91_PMC_PRES_16 (4 << 2) 82 #define AT91_PMC_PRES_32 (5 << 2) 83 #define AT91_PMC_PRES_64 (6 << 2) 84 #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ 85 #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ 86 #define AT91RM9200_PMC_MDIV_2 (1 << 8) 87 #define AT91RM9200_PMC_MDIV_3 (2 << 8) 88 #define AT91RM9200_PMC_MDIV_4 (3 << 8) 89 #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ 90 #define AT91SAM9_PMC_MDIV_2 (1 << 8) 91 #define AT91SAM9_PMC_MDIV_4 (2 << 8) 92 #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ 93 #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ 94 #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ 95 #define AT91_PMC_PDIV_1 (0 << 12) 96 #define AT91_PMC_PDIV_2 (1 << 12) 97 #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ 98 #define AT91_PMC_PLLADIV2_OFF (0 << 12) 99 #define AT91_PMC_PLLADIV2_ON (1 << 12) 100 101 #define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ 102 #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ 103 #define AT91_PMC_USBS_PLLA (0 << 0) 104 #define AT91_PMC_USBS_UPLL (1 << 0) 105 #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ 106 107 #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ 108 #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ 109 #define AT91_PMC_CSSMCK_CSS (0 << 8) 110 #define AT91_PMC_CSSMCK_MCK (1 << 8) 111 112 #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ 113 #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ 114 #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ 115 #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ 116 #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 117 #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 118 #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ 119 #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ 120 #define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ 121 #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ 122 #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ 123 #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ 124 #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ 125 #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ 126 127 #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ 128 #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ 129 130 #define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ 131 132 #ifdef __cplusplus 133 } 134 #endif 135 136 #endif 137 138