1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-01-13 weety first version 9 */ 10 11 #ifndef AT91SAM9260_H 12 #define AT91SAM9260_H 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #include <rtthread.h> 19 #include "at91_aic.h" 20 #include "at91_pit.h" 21 #include "at91_pmc.h" 22 #include "at91_rstc.h" 23 #include "at91_shdwc.h" 24 #include "at91sam9260_matrix.h" 25 #include "at91_pio.h" 26 #include "at91_serial.h" 27 #include "at91_tc.h" 28 #include "at91_pdc.h" 29 #include "io.h" 30 #include "irq.h" 31 #include "gpio.h" 32 33 /* 34 * Peripheral identifiers/interrupts. 35 */ 36 #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 37 #define AT91_ID_SYS 1 /* System Peripherals */ 38 #define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ 39 #define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ 40 #define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ 41 #define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ 42 #define AT91SAM9260_ID_US0 6 /* USART 0 */ 43 #define AT91SAM9260_ID_US1 7 /* USART 1 */ 44 #define AT91SAM9260_ID_US2 8 /* USART 2 */ 45 #define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ 46 #define AT91SAM9260_ID_UDP 10 /* USB Device Port */ 47 #define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ 48 #define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ 49 #define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ 50 #define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ 51 #define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ 52 #define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ 53 #define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ 54 #define AT91SAM9260_ID_UHP 20 /* USB Host port */ 55 #define AT91SAM9260_ID_EMAC 21 /* Ethernet */ 56 #define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ 57 #define AT91SAM9260_ID_US3 23 /* USART 3 */ 58 #define AT91SAM9260_ID_US4 24 /* USART 4 */ 59 #define AT91SAM9260_ID_US5 25 /* USART 5 */ 60 #define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ 61 #define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ 62 #define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ 63 #define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ 64 #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ 65 #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ 66 67 68 /* 69 * User Peripheral physical base addresses. 70 */ 71 #define AT91SAM9260_BASE_TCB0 0xfffa0000 72 #define AT91SAM9260_BASE_TC0 0xfffa0000 73 #define AT91SAM9260_BASE_TC1 0xfffa0040 74 #define AT91SAM9260_BASE_TC2 0xfffa0080 75 #define AT91SAM9260_BASE_UDP 0xfffa4000 76 #define AT91SAM9260_BASE_MCI 0xfffa8000 77 #define AT91SAM9260_BASE_TWI 0xfffac000 78 #define AT91SAM9260_BASE_US0 0xfffb0000 79 #define AT91SAM9260_BASE_US1 0xfffb4000 80 #define AT91SAM9260_BASE_US2 0xfffb8000 81 #define AT91SAM9260_BASE_SSC 0xfffbc000 82 #define AT91SAM9260_BASE_ISI 0xfffc0000 83 #define AT91SAM9260_BASE_EMAC 0xfffc4000 84 #define AT91SAM9260_BASE_SPI0 0xfffc8000 85 #define AT91SAM9260_BASE_SPI1 0xfffcc000 86 #define AT91SAM9260_BASE_US3 0xfffd0000 87 #define AT91SAM9260_BASE_US4 0xfffd4000 88 #define AT91SAM9260_BASE_US5 0xfffd8000 89 #define AT91SAM9260_BASE_TCB1 0xfffdc000 90 #define AT91SAM9260_BASE_TC3 0xfffdc000 91 #define AT91SAM9260_BASE_TC4 0xfffdc040 92 #define AT91SAM9260_BASE_TC5 0xfffdc080 93 #define AT91SAM9260_BASE_ADC 0xfffe0000 94 #define AT91_BASE_SYS 0xffffe800 95 #define AT91SAM9260_BASE_DBGU 0xfffff200 96 97 /* 98 * System Peripherals (offset from AT91_BASE_SYS) 99 */ 100 #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 101 #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 102 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 103 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 104 #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 105 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 106 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) 107 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) 108 #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) 109 #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) 110 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 111 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 112 #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 113 #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) 114 #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) 115 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 116 #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 117 118 119 /* 120 * Internal Memory. 121 */ 122 #define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ 123 #define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ 124 125 #define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ 126 #define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ 127 #define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ 128 #define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ 129 130 #define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ 131 132 #define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ 133 #define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 134 135 #define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ 136 #define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ 137 138 #define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ 139 #define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ 140 #define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ 141 #define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ 142 143 #define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ 144 145 146 147 /* Serial ports */ 148 #define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ 149 150 /* External Memory Map */ 151 #define AT91_CHIPSELECT_0 0x10000000 152 #define AT91_CHIPSELECT_1 0x20000000 153 #define AT91_CHIPSELECT_2 0x30000000 154 #define AT91_CHIPSELECT_3 0x40000000 155 #define AT91_CHIPSELECT_4 0x50000000 156 #define AT91_CHIPSELECT_5 0x60000000 157 #define AT91_CHIPSELECT_6 0x70000000 158 #define AT91_CHIPSELECT_7 0x80000000 159 160 /* SDRAM */ 161 #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 162 163 /* Clocks */ 164 #define AT91_SLOW_CLOCK 32768 /* slow clock */ 165 166 167 /*****************************/ 168 /* CPU Mode */ 169 /*****************************/ 170 #define USERMODE 0x10 171 #define FIQMODE 0x11 172 #define IRQMODE 0x12 173 #define SVCMODE 0x13 174 #define ABORTMODE 0x17 175 #define UNDEFMODE 0x1b 176 #define MODEMASK 0x1f 177 #define NOINT 0xc0 178 179 struct rt_hw_register 180 { 181 rt_uint32_t r0; 182 rt_uint32_t r1; 183 rt_uint32_t r2; 184 rt_uint32_t r3; 185 rt_uint32_t r4; 186 rt_uint32_t r5; 187 rt_uint32_t r6; 188 rt_uint32_t r7; 189 rt_uint32_t r8; 190 rt_uint32_t r9; 191 rt_uint32_t r10; 192 rt_uint32_t fp; 193 rt_uint32_t ip; 194 rt_uint32_t sp; 195 rt_uint32_t lr; 196 rt_uint32_t pc; 197 rt_uint32_t cpsr; 198 rt_uint32_t ORIG_r0; 199 }; 200 201 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 202 203 extern struct clk *clk_get(const char *id); 204 extern rt_uint32_t clk_get_rate(struct clk *clk); 205 extern void rt_hw_clock_init(void); 206 207 #ifdef __cplusplus 208 } 209 #endif 210 211 #endif 212 213