1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2011-01-13 weety first version
9 */
10
11 #include <rtthread.h>
12 #include <rthw.h>
13
14 #include "board.h"
15 #include <mmu.h>
16
17 /**
18 * @addtogroup at91sam9g45
19 */
20 /*@{*/
21 #if defined(__CC_ARM)
22 extern int Image$$ER_ZI$$ZI$$Limit;
23 #define HEAP_BEGIN (&Image$$ER_ZI$$ZI$$Limit)
24 #elif (defined (__GNUC__))
25 extern unsigned char __bss_end;
26 #define HEAP_BEGIN (&__bss_end)
27 #elif (defined (__ICCARM__))
28 #pragma section=".noinit"
29 #define HEAP_BEGIN (__section_end(".noinit"))
30 #endif
31
32 #define HEAP_END (((rt_uint32_t)HEAP_BEGIN & 0xF0000000) + 0x04000000)
33
34 extern void rt_hw_interrupt_init(void);
35 extern void rt_hw_clock_init(void);
36
37 extern void rt_hw_get_clock(void);
38 extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
39 extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
40 extern void rt_dbgu_isr(void);
41
42 #define SAM9G45_BLOCK_SIZE 0x10000000 // 256M
43 #define MMU_SECTION_SIZE 0x100000 // 1M
44 #define PERIPHERALS_ADDR // 1M
45
46 #define SECTION_END(sa) ((sa) + MMU_SECTION_SIZE - 1) // sa: start address
47 #define BLOCK_END(ba) ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address
48
49 static struct mem_desc at91_mem_desc[] = { /* FIXME, hornby, to confirm MMU and memory */
50 { 0x00000000, 0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */
51 //{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB }, /* TLB for ITCM, ITCM map to address zero, 32KB */
52 //{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB }, /* TLB for DTCM, 32KB */
53 //{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB }, /* TLB for internal RAM, 64KB, we use it as global variable area */
54 //{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */
55 //{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */
56 //{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */
57 //{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB }, /* 1M external SRAM for program code and stack */
58 //{ 0x40000000, BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */
59 //{ 0x60000000, BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */
60 //{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */
61 { 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB }, /* isr */
62 { 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB }, /* 128M for main DDR-SDRAM for print data */
63 //{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */
64 };
65
66
67 #define PIT_CPIV(x) ((x) & AT91C_PITC_CPIV)
68 #define PIT_PICNT(x) (((x) & AT91C_PITC_PICNT) >> 20)
69
70 static rt_uint32_t pit_cycle; /* write-once */
71 static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
72
73 /**
74 * This function will handle rtos timer
75 */
rt_timer_handler(int vector,void * param)76 void rt_timer_handler(int vector, void *param)
77 {
78 #ifdef RT_USING_DBGU
79 if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY)
80 {
81 rt_dbgu_isr();
82 }
83 #endif
84 if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS)
85 {
86 unsigned nr_ticks;
87
88 /* Get number of ticks performed before irq, and ack it */
89 nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR));
90 while (nr_ticks--)
91 rt_tick_increase();
92 }
93 }
94
at91sam9g45_pit_reset(void)95 static void at91sam9g45_pit_reset(void)
96 {
97 /* Disable timer and irqs */
98 AT91C_BASE_PITC->PITC_PIMR = 0;
99
100 /* Clear any pending interrupts, wait for PIT to stop counting */
101 while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0)
102 ;
103
104 /* Start PIT but don't enable IRQ */
105 //AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN;
106 pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR));
107 AT91C_BASE_PITC->PITC_PIMR =
108 (pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
109 rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR));
110 }
111
112 /*
113 * Set up both clocksource and clockevent support.
114 */
at91sam9g45_pit_init(void)115 static void at91sam9g45_pit_init(void)
116 {
117 rt_uint32_t pit_rate;
118 //rt_uint32_t bits;
119
120 /*
121 * Use our actual MCK to figure out how many MCK/16 ticks per
122 * 1/HZ period (instead of a compile-time constant LATCH).
123 */
124 pit_rate = clk_get_rate(clk_get("mck")) / 16;
125 rt_kprintf("pit_rate=%dHZ\n", pit_rate);
126 pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
127
128 /* Initialize and enable the timer */
129 at91sam9g45_pit_reset();
130 }
131
132 /**
133 * This function will init pit for system ticks
134 */
rt_hw_timer_init()135 void rt_hw_timer_init()
136 {
137 at91sam9g45_pit_init();
138
139 /* install interrupt handler */
140 rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler,
141 RT_NULL, "system");
142 rt_hw_interrupt_umask(AT91C_ID_SYS);
143 }
144
at91_tc1_init()145 void at91_tc1_init()
146 {
147 AT91C_BASE_PMC->PMC_PCER = 1<<AT91C_ID_TC;
148 writel(AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE, AT91C_TCB0_BMR);
149 writel(AT91C_TC_CLKDIS, AT91C_TC0_CCR);
150 writel(AT91C_TC_CLKS_TIMER_DIV4_CLOCK, AT91C_TC0_CMR);
151 writel(0xffff, AT91C_TC0_CV);
152 }
153
154 #define BPS 115200 /* serial console port baudrate */
155
at91_usart_putc(char c)156 static void at91_usart_putc(char c)
157 {
158 while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY))
159 ;
160 AT91C_BASE_DBGU->DBGU_THR = c;
161 }
162
163 /**
164 * This function is used to display a string on console, normally, it's
165 * invoked by rt_kprintf
166 *
167 * @param str the displayed string
168 */
rt_hw_console_output(const char * str)169 void rt_hw_console_output(const char* str)
170 {
171 while (*str)
172 {
173 if (*str=='\n')
174 {
175 at91_usart_putc('\r');
176 }
177
178 at91_usart_putc(*str++);
179 }
180 }
181
rt_hw_console_init(void)182 static void rt_hw_console_init(void)
183 {
184 int div;
185 int mode = 0;
186
187 AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
188 AT91C_US_RXDIS | AT91C_US_TXDIS;
189 mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
190 AT91C_US_CHMODE_NORMAL;
191 mode |= AT91C_US_CHRL_8_BITS;
192 mode |= AT91C_US_NBSTOP_1_BIT;
193 mode |= AT91C_US_PAR_NONE;
194 AT91C_BASE_DBGU->DBGU_MR = mode;
195 div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
196 AT91C_BASE_DBGU->DBGU_BRGR = div;
197 AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;
198 }
199
200
201 /**
202 * This function will init at91sam9g45 board
203 */
rt_hw_board_init()204 void rt_hw_board_init()
205 {
206 /* initialize the system clock */
207 rt_hw_clock_init();
208
209 /* initialize console */
210 rt_hw_console_init();
211
212 /* initialize mmu */
213 rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
214
215 /* initialize hardware interrupt */
216 rt_hw_interrupt_init();
217
218 /* initialize early device */
219 #ifdef RT_USING_COMPONENTS_INIT
220 rt_components_board_init();
221 #endif
222
223 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
224 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
225 #endif
226 /* initialize timer0 */
227 rt_hw_timer_init();
228
229 /* initialize board */
230 #ifdef RT_USING_HEAP
231 rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
232 #endif
233 }
234
235 /*@}*/
236