1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2015-04-14     ArdaFu      first version
9  */
10 
11 /* write register a=address, v=value */
12 #define write_reg(a,v)      (*(volatile unsigned int *)(a) = (v))
13 /* Processor Reset */
14 #define AT91C_RSTC_PROCRST   (1 << 0)
15 #define AT91C_RSTC_PERRST    (1 << 2)
16 #define AT91C_RSTC_KEY       (0xa5 << 24)
17 #define AT91C_MATRIX_BASE    (0XFFFFEE00)
18 /* Master Remap Control Register */
19 #define AT91C_MATRIX_MRCR    (AT91C_MATRIX_BASE + 0x100)
20 /* Remap Command for AHB Master 0 (ARM926EJ-S InSTRuction Master) */
21 #define AT91C_MATRIX_RCB0    (1 << 0)
22 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
23 #define AT91C_MATRIX_RCB1    (1 << 1)
24 
25 #define AT91C_AIC_BASE       (0XFFFFF000)
26 /* Interrupt DisaBLe Command Register */
27 #define AT91C_AIC_IDCR       (AT91C_AIC_BASE + 0x124)
28 /* Interrupt Clear Command Register */
29 #define AT91C_AIC_ICCR       (AT91C_AIC_BASE + 0x128)
30 
31 #define AT91C_WDT_BASE       (0XFFFFFD40)
32 #define AT91C_WDT_CR         (AT91C_WDT_BASE + 0x00)
33 #define AT91C_WDT_CR_KEY     (0xA5000000)
34 #define AT91C_WDT_CR_WDRSTT  (0x00000001)
35 #define AT91C_WDT_MR         (AT91C_WDT_BASE + 0x04)
36 #define AT91C_WDT_MR_WDDIS   (0x00008000)
37 
rt_low_level_init(void)38 void rt_low_level_init(void)
39 {
40     // Mask all IRQs by clearing all bits in the INTMRS
41     write_reg(AT91C_AIC_IDCR, 0xFFFFFFFF);
42     write_reg(AT91C_AIC_ICCR, 0xFFFFFFFF);
43     // Remap internal ram to 0x00000000 Address
44     write_reg(AT91C_MATRIX_MRCR, AT91C_MATRIX_RCB0 | AT91C_MATRIX_RCB1);
45     // Disable the watchdog
46     //write_reg(AT91C_WDT_CR, AT91C_WDT_CR_KEY|AT91C_WDT_CR_WDRSTT);
47     //write_reg(AT91C_WDT_MR, AT91C_WDT_MR_WDDIS);
48 }
49 
50