1 /*****************************************************************************
2 *
3 * \file
4 *
5 * \brief Power Manager driver.
6 *
7 * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
8 *
9 * \asf_license_start
10 *
11 * \page License
12 *
13 * Subject to your compliance with these terms, you may use Microchip
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32 *
33 *****************************************************************************/
34 /*
35 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
36 */
37
38
39 #ifndef _PM_H_
40 #define _PM_H_
41
42 /**
43 * \defgroup group_avr32_drivers_pm CPU - PM - Power Manager
44 *
45 * The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and resets in the device.
46 *
47 * \{
48 */
49
50 #include <avr32/io.h>
51 #include "compiler.h"
52 #include "preprocessor.h"
53
54
55 /*! \name Sleep Functions
56 */
57 //! @{
58
59 /*! \brief Sets the MCU in the specified sleep mode.
60 *
61 * \param mode Sleep mode:
62 * \arg \c AVR32_PM_SMODE_IDLE: Idle;
63 * \arg \c AVR32_PM_SMODE_FROZEN: Frozen;
64 * \arg \c AVR32_PM_SMODE_STANDBY: Standby;
65 * \arg \c AVR32_PM_SMODE_STOP: Stop;
66 * \arg \c AVR32_PM_SMODE_DEEP_STOP: DeepStop;
67 * \arg \c AVR32_PM_SMODE_STATIC: Static.
68 */
69 #define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
70
71 /*! \brief Enable one or several asynchronous wake-up source.
72 *
73 * \param awen_mask Mask of asynchronous wake-up sources (use one of the defines
74 * AVR32_PM_AWEN_xxxxWEN_MASK in the part-specific header file under
75 * "toolchain folder"/avr32/inc(lude)/avr32/)
76 */
pm_asyn_wake_up_enable(unsigned long awen_mask)77 __always_inline static void pm_asyn_wake_up_enable(unsigned long awen_mask)
78 {
79 AVR32_PM.awen |= awen_mask;
80 }
81
82 /*! \brief Disable one or several asynchronous wake-up sources
83 *
84 * \param awen_mask Mask of asynchronous wake-up sources (use one of the defines
85 * AVR32_PM_AWEN_xxxxWEN_MASK in the part-specific header file under
86 * "toolchain folder"/avr32/inc(lude)/avr32/)
87 */
pm_asyn_wake_up_disable(unsigned long awen_mask)88 __always_inline static void pm_asyn_wake_up_disable(unsigned long awen_mask)
89 {
90 AVR32_PM.awen &= ~awen_mask;
91 }
92
93 //! @}
94
95
96 //! Input and output parameters when initializing PM clocks using pm_configure_clocks().
97 typedef struct
98 {
99 //! CPU frequency (input/output argument).
100 unsigned long cpu_f;
101
102 //! PBA frequency (input/output argument).
103 unsigned long pba_f;
104
105 //! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).
106 unsigned long osc0_f;
107
108 //! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
109 unsigned long osc0_startup;
110 } pm_freq_param_t;
111
112 #define PM_FREQ_STATUS_FAIL (-1)
113 #define PM_FREQ_STATUS_OK (0)
114
115
116 /*! \brief Gets the MCU reset cause.
117 *
118 * \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).
119 *
120 * \return The MCU reset cause which can be masked with the
121 * \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.
122 */
pm_get_reset_cause(volatile avr32_pm_t * pm)123 __always_inline static unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
124 {
125 return pm->rcause;
126 }
127
128
129 /*!
130 * \brief This function will enable the external clock mode of the oscillator 0.
131 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
132 */
133 extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);
134
135
136 /*!
137 * \brief This function will enable the crystal mode of the oscillator 0.
138 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
139 * \param fosc0 Oscillator 0 crystal frequency (Hz)
140 */
141 extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);
142
143
144 /*!
145 * \brief This function will enable the oscillator 0 to be used with a startup time.
146 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
147 * \param startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
148 */
149 extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);
150
151
152 /*!
153 * \brief This function will disable the oscillator 0.
154 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
155 */
156 extern void pm_disable_clk0(volatile avr32_pm_t *pm);
157
158
159 /*!
160 * \brief This function will enable the oscillator 0 to be used with no startup time.
161 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
162 * \param startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
163 */
164 extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
165
166
167 /*!
168 * \brief This function will wait until the Osc0 clock is ready.
169 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
170 */
171 extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);
172
173
174 /*!
175 * \brief This function will enable the external clock mode of the oscillator 1.
176 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
177 */
178 extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);
179
180
181 /*!
182 * \brief This function will enable the crystal mode of the oscillator 1.
183 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
184 * \param fosc1 Oscillator 1 crystal frequency (Hz)
185 */
186 extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);
187
188
189 /*!
190 * \brief This function will enable the oscillator 1 to be used with a startup time.
191 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
192 * \param startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
193 */
194 extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);
195
196
197 /*!
198 * \brief This function will disable the oscillator 1.
199 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
200 */
201 extern void pm_disable_clk1(volatile avr32_pm_t *pm);
202
203
204 /*!
205 * \brief This function will enable the oscillator 1 to be used with no startup time.
206 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
207 * \param startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
208 */
209 extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
210
211
212 /*!
213 * \brief This function will wait until the Osc1 clock is ready.
214 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
215 */
216 extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);
217
218
219 /*!
220 * \brief This function will enable the external clock mode of the 32-kHz oscillator.
221 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
222 */
223 extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);
224
225
226 /*!
227 * \brief This function will enable the crystal mode of the 32-kHz oscillator.
228 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
229 */
230 extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);
231
232
233 /*!
234 * \brief This function will enable the oscillator 32 to be used with a startup time.
235 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
236 * \param startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
237 */
238 extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);
239
240
241 /*!
242 * \brief This function will disable the oscillator 32.
243 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
244 */
245 extern void pm_disable_clk32(volatile avr32_pm_t *pm);
246
247
248 /*!
249 * \brief This function will enable the oscillator 32 to be used with no startup time.
250 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
251 * \param startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
252 */
253 extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
254
255
256 /*!
257 * \brief This function will wait until the osc32 clock is ready.
258 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
259 */
260 extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);
261
262
263 /*!
264 * \brief This function will select all the power manager clocks.
265 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
266 * \param pbadiv Peripheral Bus A clock divisor enable
267 * \param pbasel Peripheral Bus A select
268 * \param pbbdiv Peripheral Bus B clock divisor enable
269 * \param pbbsel Peripheral Bus B select
270 * \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
271 * \param hsbsel High Speed Bus select (CPU clock = HSB clock )
272 */
273 extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);
274
275
276 /*!
277 * \brief This function will setup a generic clock.
278 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
279 * \param gc generic clock number (0 for gc0...)
280 * \param osc_or_pll Use OSC (=0) or PLL (=1)
281 * \param pll_osc Select Osc0/PLL0 or Osc1/PLL1
282 * \param diven Generic clock divisor enable
283 * \param div Generic clock divisor
284 */
285 extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);
286
287
288 /*!
289 * \brief This function will enable a generic clock.
290 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
291 * \param gc generic clock number (0 for gc0...)
292 */
293 extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);
294
295
296 /*!
297 * \brief This function will disable a generic clock.
298 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
299 * \param gc generic clock number (0 for gc0...)
300 */
301 extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);
302
303
304 /*!
305 * \brief This function will setup a PLL.
306 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
307 * \param pll PLL number(0 for PLL0, 1 for PLL1)
308 * \param mul PLL MUL in the PLL formula
309 * \param div PLL DIV in the PLL formula
310 * \param osc OSC number (0 for osc0, 1 for osc1)
311 * \param lockcount PLL lock count
312 */
313 extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);
314
315
316 /*!
317 * \brief This function will set a PLL option.
318 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
319 * \param pll PLL number(0 for PLL0, 1 for PLL1)
320 * \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
321 * \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
322 * \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
323 */
324 extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable);
325
326
327 /*!
328 * \brief This function will get a PLL option.
329 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
330 * \param pll PLL number(0 for PLL0, 1 for PLL1)
331 * \return Option
332 */
333 extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);
334
335
336 /*!
337 * \brief This function will enable a PLL.
338 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
339 * \param pll PLL number(0 for PLL0, 1 for PLL1)
340 */
341 extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);
342
343
344 /*!
345 * \brief This function will disable a PLL.
346 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
347 * \param pll PLL number(0 for PLL0, 1 for PLL1)
348 */
349 extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);
350
351
352 /*!
353 * \brief This function will wait for PLL0 locked
354 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
355 */
356 extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);
357
358
359 /*!
360 * \brief This function will wait for PLL1 locked
361 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
362 */
363 extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);
364
365
366 /*!
367 * \brief This function returns the cksel (Clock Select).
368 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
369 * \param p_cksel output cksel value
370 */
371 extern void pm_cksel_get(volatile avr32_pm_t *pm, unsigned long* p_cksel);
372
373
374 /*!
375 * \brief This function set the cksel (Clock Select).
376 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
377 * \param cksel The cksel value.
378 */
379 extern void pm_cksel_set(volatile avr32_pm_t *pm, unsigned long cksel);
380
381
382 /*!
383 * \brief This function returns the power manager main clock.
384 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
385 * \retval The main clock value.
386 */
387 extern unsigned long pm_get_clock(volatile avr32_pm_t *pm);
388
389
390 /*!
391 * \brief This function will switch the power manager main clock.
392 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
393 * \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.
394 */
395 extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);
396
397
398 /*!
399 * \brief Switch main clock to clock Osc0 (crystal mode)
400 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
401 * \param fosc0 Oscillator 0 crystal frequency (Hz)
402 * \param startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
403 */
404 extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);
405
406
407 /*! \brief Enables the Brown-Out Detector interrupt.
408 *
409 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
410 */
411 extern void pm_bod_enable_irq(volatile avr32_pm_t *pm);
412
413
414 /*! \brief Disables the Brown-Out Detector interrupt.
415 *
416 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
417 */
418 extern void pm_bod_disable_irq(volatile avr32_pm_t *pm);
419
420
421 /*! \brief Clears the Brown-Out Detector interrupt flag.
422 *
423 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
424 */
425 extern void pm_bod_clear_irq(volatile avr32_pm_t *pm);
426
427
428 /*! \brief Gets the Brown-Out Detector interrupt flag.
429 *
430 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
431 *
432 * \retval 0 No BOD interrupt.
433 * \retval 1 BOD interrupt pending.
434 */
435 extern unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm);
436
437
438 /*! \brief Gets the Brown-Out Detector interrupt enable status.
439 *
440 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
441 *
442 * \retval 0 BOD interrupt disabled.
443 * \retval 1 BOD interrupt enabled.
444 */
445 extern unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm);
446
447
448 /*! \brief Gets the triggering threshold of the Brown-Out Detector.
449 *
450 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
451 *
452 * \return Triggering threshold of the BOD. See the electrical characteristics
453 * in the part datasheet for actual voltage levels.
454 */
455 extern unsigned long pm_bod_get_level(volatile avr32_pm_t *pm);
456
457
458 /*!
459 * \brief Read the content of the PM GPLP registers
460 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
461 * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
462 *
463 * \return The content of the chosen GPLP register.
464 */
465 extern unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp);
466
467
468 /*!
469 * \brief Write into the PM GPLP registers
470 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
471 * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
472 * \param value Value to write
473 */
474 extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value);
475
476
477 /*! \brief Enable the clock of a module.
478 *
479 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
480 * \param module The module to clock (use one of the defines in the part-specific
481 * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
482 * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
483 *
484 * \return Status.
485 * \retval 0 Success.
486 * \retval <0 An error occurred.
487 */
488 extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module);
489
490 /*! \brief Disable the clock of a module.
491 *
492 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
493 * \param module The module to shut down (use one of the defines in the part-specific
494 * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
495 * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
496 *
497 * \return Status.
498 * \retval 0 Success.
499 * \retval <0 An error occurred.
500 */
501 extern long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module);
502
503
504
505 /*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
506 * according to the user wishes.
507 *
508 * This function needs some parameters stored in a pm_freq_param_t structure:
509 * - cpu_f and pba_f are the wanted frequencies,
510 * - osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0),
511 * - osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP).
512 *
513 * The function will then configure the clocks using the following rules:
514 * - It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order
515 * to satisfy the CPU frequency,
516 * - It optimizes the configuration depending the various divide stages,
517 * - Then, the PBA frequency is configured from the CPU freq.
518 * - Note that HSB and PBB are configured with the same frequency as CPU.
519 * - Note also that the number of wait states of the flash read accesses is automatically set-up depending
520 * the CPU frequency. As a consequence, the application needs the FLASHC driver to compile.
521 *
522 * The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
523 *
524 * \param param pointer on the configuration structure.
525 *
526 * \retval PM_FREQ_STATUS_OK Mode successfully initialized.
527 * \retval PM_FREQ_STATUS_FAIL The configuration can not be done.
528 */
529 extern int pm_configure_clocks(pm_freq_param_t *param);
530
531
532 /*! \brief Automatically configure the USB clock.
533 *
534 * USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming
535 * a 12 MHz crystal is connected to it.
536 */
537 extern void pm_configure_usb_clock(void);
538
539 /**
540 * \}
541 */
542
543 #endif // _PM_H_
544