1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2012-11-20 Bernard the first version
9 */
10
11 #include <rthw.h>
12 #include <rtthread.h>
13 #include <finsh.h>
14
15 #include "board.h"
16 #include <mmu.h>
17 #include <interrupt.h>
18
19 #define TIMER_HW_BASE AM33XX_DMTIMER_7_REGS
20
21 #define DMTIMER_TCLR_AR (0x00000002u)
22 #define DMTIMER_TCLR_CE (0x00000040u)
23 #define DMTIMER_TCLR_PRE (0x00000020u)
24 #define DMTIMER_TCLR_ST (0x00000001u)
25 #define DMTIMER_IRQENABLE_SET_OVF_EN_FLAG (0x00000002u)
26 #define DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG (0x00000002u)
27
28 #define CM_DPLL_CLKSEL_CLK_CLKSEL (0x00000003u)
29 #define CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3 (0x2u)
30
31 #define CM_PER_CLKCTRL_MODULEMODE_ENABLE (0x2u)
32 #define CM_PER_CLKCTRL_MODULEMODE (0x00000003u)
33
34 #define CM_PER_CLKCTRL_IDLEST (0x00030000u)
35 #define CM_PER_CLKCTRL_IDLEST_FUNC (0x0u)
36
37 #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
38 #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK (0x00004000u)
39 #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK (1<<13)
40
rt_hw_timer_isr(int vector,void * param)41 static void rt_hw_timer_isr(int vector, void* param)
42 {
43 rt_tick_increase();
44
45 DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
46 }
47
timer_clk_init(void)48 static void timer_clk_init(void)
49 {
50 unsigned long prcm_base;
51
52 prcm_base = AM33XX_PRCM_REGS;
53
54 /* software forced wakeup */
55 CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2;
56
57 /* Waiting for the L4LS clock */
58 while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
59 ;
60
61 /* Select the clock source for the Timer2 instance. */
62 CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL);
63 /* 32k clock source */
64 CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3;
65
66 while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) !=
67 CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3);
68
69 /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */
70 CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE;
71
72 /* Waiting for MODULEMODE field to reflect the written value. */
73 while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) !=
74 CM_PER_CLKCTRL_MODULEMODE_ENABLE);
75
76 /*
77 * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register
78 * for the module is fully functional.
79 */
80 while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) !=
81 CM_PER_CLKCTRL_IDLEST_FUNC);
82
83 /* Waiting for the L4LS clock */
84 while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK));
85 /* Waiting for the TIMER7 clock */
86 while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK));
87 }
88
rt_hw_timer_init(void)89 int rt_hw_timer_init(void)
90 {
91 rt_uint32_t counter;
92
93 timer_clk_init();
94
95 /* soft reset the timer */
96 DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1;
97 while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1)
98 ;
99
100 /* calculate count */
101 counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND);
102
103 /* set initial count */
104 DMTIMER_TCRR(TIMER_HW_BASE) = counter;
105 /* set reload count */
106 DMTIMER_TLDR(TIMER_HW_BASE) = counter;
107
108 /* set mode: auto reload */
109 DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR;
110
111 /* interrupt enable for match */
112 DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG;
113 DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
114
115 rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick");
116 rt_hw_interrupt_control(TINT7, 0, 0);
117 rt_hw_interrupt_umask(TINT7);
118
119 while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
120 ;
121
122 /* start timer */
123 DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST;
124
125 while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
126 ;
127
128 return 0;
129 }
130 INIT_BOARD_EXPORT(rt_hw_timer_init);
131
132 /**
133 * This function will initialize beaglebone board
134 */
rt_hw_board_init(void)135 void rt_hw_board_init(void)
136 {
137 rt_hw_mmu_init();
138
139 /* init hardware interrupt */
140 rt_hw_interrupt_init();
141
142 /* Heap initialization */
143 #if defined(RT_USING_HEAP)
144 rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
145 #endif
146
147 rt_components_board_init();
148 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
149 }
150
rt_hw_cpu_reset(void)151 void rt_hw_cpu_reset(void)
152 {
153 unsigned long prcm_base = AM33XX_PRCM_REGS;
154
155 REG32(PRM_DEVICE(prcm_base)) = 0x1;
156 RT_ASSERT(0);
157 }
158 MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu);
159