1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2013-07-06 Bernard the first version
9 * 2014-01-11 RTsien support UART0 to UART5 straightly
10 */
11
12 #include <rthw.h>
13 #include <rtthread.h>
14 #include <rtdevice.h>
15
16 #include <am33xx.h>
17 #include <interrupt.h>
18 #include "uart.h"
19 #include "uart_reg.h"
20
21 struct am33xx_uart
22 {
23 unsigned long base;
24 int irq;
25 };
26
am33xx_uart_isr(int irqno,void * param)27 static void am33xx_uart_isr(int irqno, void* param)
28 {
29 rt_uint32_t iir;
30 struct am33xx_uart* uart;
31 struct rt_serial_device *serial;
32
33 serial = (struct rt_serial_device*)param;
34 uart = (struct am33xx_uart *)serial->parent.user_data;
35
36 iir = UART_IIR_REG(uart->base);
37
38 if ((iir & (0x02 << 1)) || (iir & (0x6 << 1)))
39 {
40 rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
41 }
42 }
43
44 #define NOT_IMPLEMENTED() RT_ASSERT(0)
45
am33xx_configure(struct rt_serial_device * serial,struct serial_configure * cfg)46 static rt_err_t am33xx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
47 {
48 struct am33xx_uart* uart;
49 unsigned long base;
50
51 RT_ASSERT(serial != RT_NULL);
52 uart = (struct am33xx_uart *)serial->parent.user_data;
53 RT_ASSERT(uart);
54 base = uart->base;
55
56 #define __LCR UART_LCR_REG(base)
57
58 if (cfg->data_bits == DATA_BITS_8)
59 __LCR |= 3;
60 else
61 NOT_IMPLEMENTED();
62
63 if (cfg->stop_bits == STOP_BITS_1)
64 __LCR &= ~(1<<2);
65 else
66 __LCR |= (1<<2);
67
68 if (cfg->parity == PARITY_NONE)
69 __LCR &= ~(1<<3);
70 else
71 __LCR |= (1<<3);
72
73 __LCR |= (1<<7);
74 if (cfg->baud_rate == BAUD_RATE_115200)
75 {
76 UART_DLL_REG(base) = 26;
77 UART_DLH_REG(base) = 0;
78 }
79 else if (cfg->baud_rate == BAUD_RATE_9600)
80 {
81 UART_DLL_REG(base) = 0x38;
82 UART_DLH_REG(base) = 1;
83 }
84 else
85 {
86 NOT_IMPLEMENTED();
87 }
88 __LCR &= ~(1<<7);
89
90 UART_MDR1_REG(base) = 0;
91 UART_MDR2_REG(base) = 0;
92
93 #undef __LCR
94 return RT_EOK;
95 }
96
am33xx_control(struct rt_serial_device * serial,int cmd,void * arg)97 static rt_err_t am33xx_control(struct rt_serial_device *serial, int cmd, void *arg)
98 {
99 struct am33xx_uart* uart;
100
101 RT_ASSERT(serial != RT_NULL);
102 uart = (struct am33xx_uart *)serial->parent.user_data;
103
104 switch (cmd)
105 {
106 case RT_DEVICE_CTRL_CLR_INT:
107 /* disable rx irq */
108 rt_hw_interrupt_mask(uart->irq);
109 break;
110 case RT_DEVICE_CTRL_SET_INT:
111 /* enable rx irq */
112 rt_hw_interrupt_umask(uart->irq);
113 break;
114 }
115
116 return RT_EOK;
117 }
118
printkc(char c)119 int printkc(char c)
120 {
121 int base = 0xf9e09000;
122
123 while (!(UART_LSR_REG(base) & 0x20));
124 UART_THR_REG(base) = c;
125
126 return 1;
127 }
128
am33xx_putc(struct rt_serial_device * serial,char c)129 static int am33xx_putc(struct rt_serial_device *serial, char c)
130 {
131 struct am33xx_uart* uart;
132
133 RT_ASSERT(serial != RT_NULL);
134 uart = (struct am33xx_uart *)serial->parent.user_data;
135
136 while (!(UART_LSR_REG(uart->base) & 0x20));
137 UART_THR_REG(uart->base) = c;
138
139 return 1;
140 }
141
am33xx_getc(struct rt_serial_device * serial)142 static int am33xx_getc(struct rt_serial_device *serial)
143 {
144 int ch;
145 struct am33xx_uart* uart;
146
147 RT_ASSERT(serial != RT_NULL);
148 uart = (struct am33xx_uart *)serial->parent.user_data;
149
150 ch = -1;
151 if (UART_LSR_REG(uart->base) & 0x01)
152 {
153 ch = UART_RHR_REG(uart->base) & 0xff;
154 }
155
156 return ch;
157 }
158
159 static const struct rt_uart_ops am33xx_uart_ops =
160 {
161 am33xx_configure,
162 am33xx_control,
163 am33xx_putc,
164 am33xx_getc,
165 };
166
167 /* UART device driver structure */
168 #ifdef RT_USING_UART0
169 struct am33xx_uart uart0 =
170 {
171 UART0_BASE,
172 UART0_INT,
173 };
174 struct rt_serial_device serial0;
175 #endif
176
177 #ifdef RT_USING_UART1
178 struct am33xx_uart uart1 =
179 {
180 UART1_BASE,
181 UART1_INT,
182 };
183 struct rt_serial_device serial1;
184 #endif
185
186 #ifdef RT_USING_UART2
187 struct am33xx_uart uart2 =
188 {
189 UART2_BASE,
190 UART2_INT,
191 };
192 struct rt_serial_device serial2;
193 #endif
194
195 #ifdef RT_USING_UART3
196 struct am33xx_uart uart3 =
197 {
198 UART3_BASE,
199 UART3_INT,
200 };
201 struct rt_serial_device serial3;
202 #endif
203
204 #ifdef RT_USING_UART4
205 struct am33xx_uart uart4 =
206 {
207 UART4_BASE,
208 UART4_INT,
209 };
210 struct rt_serial_device serial4;
211 #endif
212
213 #ifdef RT_USING_UART5
214 struct am33xx_uart uart5 =
215 {
216 UART5_BASE,
217 UART5_INT,
218 };
219 struct rt_serial_device serial5;
220 #endif
221
222 #define write_reg(base, value) *(int*)(base) = value
223 #define read_reg(base) *(int*)(base)
224
225 #define PRM_PER_INTRANSLATION (1 << 20)
226 #define PRM_PER_POWSTATEOFF (0)
227 #define PRM_PER_PERMEMSTATEOFF (0)
228
poweron_per_domain(void)229 static void poweron_per_domain(void)
230 {
231 unsigned long prcm_base;
232 unsigned long prm_state;
233
234 prcm_base = AM33XX_PRCM_REGS;
235
236 /* wait for ongoing translations */
237 for (prm_state = PRM_PER_PWRSTST_REG(prcm_base);
238 prm_state & PRM_PER_INTRANSLATION;
239 prm_state = PRM_PER_PWRSTST_REG(prcm_base))
240 ;
241
242 /* check power state */
243 if ((prm_state & 0x03) == PRM_PER_POWSTATEOFF)
244 /* power on PER domain */
245 PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3;
246
247 /* check per mem state */
248 if ((prm_state & 0x03) == PRM_PER_PERMEMSTATEOFF)
249 /* power on PER domain */
250 PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3 << 25;
251
252 while (PRM_PER_PWRSTST_REG(prcm_base) & PRM_PER_INTRANSLATION)
253 ;
254 }
255
start_uart_clk(void)256 static void start_uart_clk(void)
257 {
258 unsigned long prcm_base;
259
260 prcm_base = AM33XX_PRCM_REGS;
261
262 #if defined(RT_USING_UART1) || defined(RT_USING_UART2) || defined(RT_USING_UART3) || defined(RT_USING_UART4) || defined(RT_USING_UART5)
263 /* software forced wakeup */
264 CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2;
265
266 /* Waiting for the L4LS clock */
267 while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
268 ;
269
270 /* enable uart1 */
271 #ifdef RT_USING_UART1
272 CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2;
273 /* wait for uart1 clk */
274 while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
275 ;
276 #endif
277
278 #ifdef RT_USING_UART2
279 CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2;
280 /* wait for uart2 clk */
281 while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
282 ;
283 #endif
284
285 #ifdef RT_USING_UART3
286 CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2;
287 /* wait for uart3 clk */
288 while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
289 ;
290 #endif
291
292 #ifdef RT_USING_UART4
293 CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2;
294 /* wait for uart4 clk */
295 while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
296 ;
297 #endif
298
299 #ifdef RT_USING_UART5
300 CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2;
301 /* wait for uart5 clk */
302 while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
303 ;
304 #endif
305
306 /* Waiting for the L4LS UART clock */
307 while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10)))
308 ;
309 #endif
310
311 #ifdef RT_USING_UART0
312 /* software forced wakeup */
313 CM_WKUP_CLKSTCTRL_REG(prcm_base) |= 0x2;
314
315 /* Waiting for the L4_WKUP clock */
316 while (!(CM_WKUP_CLKSTCTRL_REG(prcm_base) & (1<<2)))
317 ;
318
319 /* enable uart0 */
320 CM_WKUP_UART0_CLKCTRL_REG(prcm_base) |= 0x2;
321 /* wait for uart0 clk */
322 while ((CM_WKUP_UART0_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
323 ;
324
325 /* Waiting for the L4_WKUP UART0 clock */
326 while (!(CM_WKUP_CLKSTCTRL_REG(prcm_base) & (1<<12)))
327 ;
328 #endif
329 }
330
config_pinmux(void)331 static void config_pinmux(void)
332 {
333 unsigned long ctlm_base;
334
335 ctlm_base = AM33XX_CTLM_REGS;
336
337 /* make sure the pin mux is OK for uart */
338 #ifdef RT_USING_UART0
339 REG32(ctlm_base + 0x800 + 0x170) = 0x20;
340 REG32(ctlm_base + 0x800 + 0x174) = 0x00;
341 #endif
342
343 #ifdef RT_USING_UART1
344 REG32(ctlm_base + 0x800 + 0x180) = 0x20;
345 REG32(ctlm_base + 0x800 + 0x184) = 0x00;
346 #endif
347
348 #ifdef RT_USING_UART2
349 REG32(ctlm_base + 0x800 + 0x150) = 0x20;
350 REG32(ctlm_base + 0x800 + 0x154) = 0x00;
351 #endif
352
353 #ifdef RT_USING_UART3
354 REG32(ctlm_base + 0x800 + 0x164) = 0x01;
355 #endif
356
357 #ifdef RT_USING_UART4
358 REG32(ctlm_base + 0x800 + 0x070) = 0x26;
359 REG32(ctlm_base + 0x800 + 0x074) = 0x06;
360 #endif
361
362 #ifdef RT_USING_UART5
363 REG32(ctlm_base + 0x800 + 0x0C4) = 0x24;
364 REG32(ctlm_base + 0x800 + 0x0C0) = 0x04;
365 #endif
366 }
367
rt_hw_serial_init(void)368 int rt_hw_serial_init(void)
369 {
370 struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
371
372 poweron_per_domain();
373 start_uart_clk();
374 config_pinmux();
375
376 #ifdef RT_USING_UART0
377 serial0.ops = &am33xx_uart_ops;
378 serial0.config = config;
379
380 /* enable RX interrupt */
381 UART_IER_REG(uart0.base) = 0x01;
382 /* install ISR */
383 rt_hw_interrupt_install(uart0.irq, am33xx_uart_isr, &serial0, "uart0");
384 rt_hw_interrupt_control(uart0.irq, 0, 0);
385 rt_hw_interrupt_mask(uart0.irq);
386 /* register UART0 device */
387 rt_hw_serial_register(&serial0, "uart0",
388 RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
389 &uart0);
390 #endif
391
392 #ifdef RT_USING_UART1
393 serial1.ops = &am33xx_uart_ops;
394 serial1.config = config;
395 /* enable RX interrupt */
396 UART_IER_REG(uart1.base) = 0x01;
397 /* install ISR */
398 rt_hw_interrupt_install(uart1.irq, am33xx_uart_isr, &serial1, "uart1");
399 rt_hw_interrupt_control(uart1.irq, 0, 0);
400 rt_hw_interrupt_mask(uart1.irq);
401 /* register UART0 device */
402 rt_hw_serial_register(&serial1, "uart1",
403 RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
404 &uart1);
405 #endif
406
407 #ifdef RT_USING_UART2
408 serial2.ops = &am33xx_uart_ops;
409 serial2.config = config;
410 /* enable RX interrupt */
411 UART_IER_REG(uart2.base) = 0x01;
412 /* install ISR */
413 rt_hw_interrupt_install(uart2.irq, am33xx_uart_isr, &serial2, "uart2");
414 rt_hw_interrupt_control(uart2.irq, 0, 0);
415 rt_hw_interrupt_mask(uart2.irq);
416 /* register UART2 device */
417 rt_hw_serial_register(&serial2, "uart2",
418 RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
419 &uart2);
420 #endif
421
422 #ifdef RT_USING_UART3
423 serial3.ops = &am33xx_uart_ops;
424 serial3.config = config;
425 /* enable RX interrupt */
426 UART_IER_REG(uart3.base) = 0x01;
427 /* install ISR */
428 rt_hw_interrupt_install(uart3.irq, am33xx_uart_isr, &serial3, "uart3");
429 rt_hw_interrupt_control(uart3.irq, 0, 0);
430 rt_hw_interrupt_mask(uart3.irq);
431 /* register UART3 device */
432 rt_hw_serial_register(&serial3, "uart3",
433 RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
434 &uart3);
435 #endif
436
437 #ifdef RT_USING_UART4
438 /* use 9600bps for GDB stub. */
439 config.baud_rate = BAUD_RATE_9600;
440
441 serial4.ops = &am33xx_uart_ops;
442 serial4.config = config;
443 /* enable RX interrupt */
444 UART_IER_REG(uart4.base) = 0x00;
445 /* install ISR */
446 rt_hw_interrupt_install(uart4.irq, am33xx_uart_isr, &serial4, "uart4");
447 rt_hw_interrupt_control(uart4.irq, 0, 0);
448 rt_hw_interrupt_mask(uart4.irq);
449 /* register UART4 device */
450 rt_hw_serial_register(&serial4, "uart4",
451 RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
452 &uart4);
453 #endif
454
455 #ifdef RT_USING_UART5
456 config.baud_rate = BAUD_RATE_115200;
457
458 serial5.ops = &am33xx_uart_ops;
459 serial5.config = config;
460 /* enable RX interrupt */
461 UART_IER_REG(uart5.base) = 0x01;
462 /* install ISR */
463 rt_hw_interrupt_install(uart5.irq, am33xx_uart_isr, &serial5, "uart5");
464 rt_hw_interrupt_control(uart5.irq, 0, 0);
465 rt_hw_interrupt_mask(uart5.irq);
466 /* register UART4 device */
467 rt_hw_serial_register(&serial5, "uart5",
468 RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
469 &uart5);
470 #endif
471
472 return 0;
473 }
474 INIT_BOARD_EXPORT(rt_hw_serial_init);
475