1 /*
2  * Copyright (c) 2020-2021, Bluetrum Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author            Notes
8  * 2020-11-30     greedyhao         first version
9  */
10 
11 #ifndef DEV_SDIO_H__
12 #define DEV_SDIO_H__
13 
14 #include "drv_common.h"
15 #include "board.h"
16 #include "drivers/dev_mmcsd_core.h"
17 #include "drivers/dev_sdio.h"
18 
19 #define SDIO_BUFF_SIZE       1024
20 #define SDIO_ALIGN_LEN       32
21 
22 #ifndef SDIO_BASE_ADDRESS
23 #define SDIO_BASE_ADDRESS    (0x40012800U)
24 #endif
25 
26 #ifndef SDIO_CLOCK_FREQ
27 #define SDIO_CLOCK_FREQ      (48U * 1000 * 1000)
28 #endif
29 
30 #ifndef SDIO_BUFF_SIZE
31 #define SDIO_BUFF_SIZE       (4096)
32 #endif
33 
34 #ifndef SDIO_ALIGN_LEN
35 #define SDIO_ALIGN_LEN       (32)
36 #endif
37 
38 #ifndef SDIO_MAX_FREQ
39 #define SDIO_MAX_FREQ        (24 * 1000 * 1000)
40 #endif
41 
42 
43 #define HW_SDIO_CON_
44 #define HW_SDIO_CON_CFLAG                       (0x01u << 12)   /*!< 0:send command or received response not finish \
45                                                                      1:send command or received response finish     */
46 #define HW_SDIO_CON_DFLAG                       (0x01u << 13)   /*!< 0:send or received data not finish             \
47                                                                      1:send or received data finish                 */
48 #define HW_SDIO_CON_CCRCE                       (0x01u << 14)   /*!< 0:command crc no error                         \
49                                                                      1:command crc error detected                   */
50 #define HW_SDIO_CON_NRPS                        (0x01u << 15)   /*!< 0:response received 1:no response received     */
51 #define HW_SDIO_CON_DCRCE                       (0x01u << 16)   /*!< 0:read data crc no error                       \
52                                                                      1:read data crc error detected                 */
53 #define HW_SDIO_CON_CRCS                        (0x07u << 17)   /*!< 101:error transmission                         \
54                                                                      010:non-erroneous transmission                 \
55                                                                      111:flash error                                */
56 #define HW_SDIO_CON_BUSY                        (0x01u << 20)   /*!< 0:device busy 1:device not busy                */
57 
58 #define HW_SDIO_ERRORS \
59     (0)
60 
61 #define HW_SDIO_POWER_OFF                      (0x00U)
62 #define HW_SDIO_POWER_UP                       (0x02U)
63 #define HW_SDIO_POWER_ON                       (0x03U)
64 
65 #define HW_SDIO_FLOW_ENABLE                    (0x01U << 14)
66 #define HW_SDIO_BUSWIDE_1B                     (0x00U << 11)
67 #define HW_SDIO_BUSWIDE_4B                     (0x01U << 11)
68 #define HW_SDIO_BUSWIDE_8B                     (0x02U << 11)
69 #define HW_SDIO_BYPASS_ENABLE                  (0x01U << 10)
70 #define HW_SDIO_IDLE_ENABLE                    (0x01U << 9)
71 #define HW_SDIO_CLK_ENABLE                     (0x01U << 8)
72 
73 #define HW_SDIO_SUSPEND_CMD                    (0x01U << 11)
74 #define HW_SDIO_CPSM_ENABLE                    (0x01U << 10)
75 #define HW_SDIO_WAIT_END                       (0x01U << 9)
76 #define HW_SDIO_WAIT_INT                       (0x01U << 8)
77 #define HW_SDIO_RESPONSE_NO                    (0x00U << 6)
78 #define HW_SDIO_RESPONSE_SHORT                 (0x01U << 6)
79 #define HW_SDIO_RESPONSE_LONG                  (0x03U << 6)
80 
81 #define HW_SDIO_DATA_LEN_MASK                  (0x01FFFFFFU)
82 
83 #define HW_SDIO_IO_ENABLE                      (0x01U << 11)
84 #define HW_SDIO_RWMOD_CK                       (0x01U << 10)
85 #define HW_SDIO_RWSTOP_ENABLE                  (0x01U << 9)
86 #define HW_SDIO_RWSTART_ENABLE                 (0x01U << 8)
87 #define HW_SDIO_DBLOCKSIZE_1                   (0x00U << 4)
88 #define HW_SDIO_DBLOCKSIZE_2                   (0x01U << 4)
89 #define HW_SDIO_DBLOCKSIZE_4                   (0x02U << 4)
90 #define HW_SDIO_DBLOCKSIZE_8                   (0x03U << 4)
91 #define HW_SDIO_DBLOCKSIZE_16                  (0x04U << 4)
92 #define HW_SDIO_DBLOCKSIZE_32                  (0x05U << 4)
93 #define HW_SDIO_DBLOCKSIZE_64                  (0x06U << 4)
94 #define HW_SDIO_DBLOCKSIZE_128                 (0x07U << 4)
95 #define HW_SDIO_DBLOCKSIZE_256                 (0x08U << 4)
96 #define HW_SDIO_DBLOCKSIZE_512                 (0x09U << 4)
97 #define HW_SDIO_DBLOCKSIZE_1024                (0x0AU << 4)
98 #define HW_SDIO_DBLOCKSIZE_2048                (0x0BU << 4)
99 #define HW_SDIO_DBLOCKSIZE_4096                (0x0CU << 4)
100 #define HW_SDIO_DBLOCKSIZE_8192                (0x0DU << 4)
101 #define HW_SDIO_DBLOCKSIZE_16384               (0x0EU << 4)
102 #define HW_SDIO_DMA_ENABLE                     (0x01U << 3)
103 #define HW_SDIO_STREAM_ENABLE                  (0x01U << 2)
104 #define HW_SDIO_TO_HOST                        (0x01U << 1)
105 #define HW_SDIO_DPSM_ENABLE                    (0x01U << 0)
106 
107 #define HW_SDIO_DATATIMEOUT                    (0xF0000000U)
108 
109 // struct ab32_sdio
110 // {};
111 
112 typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, int size);
113 typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *dst, int size);
114 typedef rt_uint32_t (*sdio_clk_get)(hal_sfr_t hw_sdio);
115 
116 struct ab32_sdio_des
117 {
118     hal_sfr_t    hw_sdio;
119     dma_txconfig txconfig;
120     dma_rxconfig rxconfig;
121     sdio_clk_get clk_get;
122 };
123 
124 struct ab32_sdio_config
125 {
126     hal_sfr_t instance;
127     // struct dma_config dma_rx, dma_tx;
128 };
129 
130 struct ab32_sdio_class
131 {
132     const struct ab32_sdio_config *cfg;
133     struct rt_mmcsd_host host;
134 };
135 
136 #endif
137