1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2023/03/15 flyingcys first version
9 */
10 #include <rthw.h>
11 #include <rtthread.h>
12
13 #include "board.h"
14 #include "drv_uart.h"
15
system_clock_init(void)16 static void system_clock_init(void)
17 {
18 #if 1
19 /* wifipll/audiopll */
20 GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | GLB_PLL_AUPLL);
21 GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M);
22 #else
23 GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
24 GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL);
25 GLB_Config_AUDIO_PLL_To_384M();
26 GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1);
27 GLB_Set_MCU_System_CLK_Div(0, 3);
28 #endif
29 CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK) / 1000000 - 1);
30 }
31
peripheral_clock_init(void)32 static void peripheral_clock_init(void)
33 {
34 PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
35 PERIPHERAL_CLOCK_SEC_ENABLE();
36 PERIPHERAL_CLOCK_DMA0_ENABLE();
37 PERIPHERAL_CLOCK_UART0_ENABLE();
38 PERIPHERAL_CLOCK_UART1_ENABLE();
39 PERIPHERAL_CLOCK_SPI0_ENABLE();
40 PERIPHERAL_CLOCK_I2C0_ENABLE();
41 PERIPHERAL_CLOCK_PWM0_ENABLE();
42 PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
43 PERIPHERAL_CLOCK_IR_ENABLE();
44 PERIPHERAL_CLOCK_I2S_ENABLE();
45 PERIPHERAL_CLOCK_USB_ENABLE();
46 PERIPHERAL_CLOCK_CAN_ENABLE();
47
48 GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
49 GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
50 GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
51 GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
52 GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
53 GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
54 GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
55 GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
56 GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3);
57
58 GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
59
60 GLB_Set_USB_CLK_From_WIFIPLL(1);
61 GLB_Swap_MCU_SPI_0_MOSI_With_MISO(0);
62 }
63
64 #ifdef BSP_USING_PSRAM
bflb_init_psram_gpio(void)65 static void bflb_init_psram_gpio(void)
66 {
67 struct bflb_device_s *gpio;
68
69 gpio = bflb_device_get_by_name("gpio");
70 for (uint8_t i = 0; i < 12; i++) {
71 bflb_gpio_init(gpio, (41 + i), GPIO_INPUT | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_0);
72 }
73 }
74
psram_winbond_default_init(void)75 static void psram_winbond_default_init(void)
76 {
77 PSRAM_Ctrl_Cfg_Type default_psram_ctrl_cfg = {
78 .vendor = PSRAM_CTRL_VENDOR_WINBOND,
79 .ioMode = PSRAM_CTRL_X8_MODE,
80 .size = PSRAM_SIZE_4MB,
81 .dqs_delay = 0xfff0,
82 };
83
84 PSRAM_Winbond_Cfg_Type default_winbond_cfg = {
85 .rst = DISABLE,
86 .clockType = PSRAM_CLOCK_DIFF,
87 .inputPowerDownMode = DISABLE,
88 .hybridSleepMode = DISABLE,
89 .linear_dis = ENABLE,
90 .PASR = PSRAM_PARTIAL_REFRESH_FULL,
91 .disDeepPowerDownMode = ENABLE,
92 .fixedLatency = DISABLE,
93 .brustLen = PSRAM_WINBOND_BURST_LENGTH_64_BYTES,
94 .brustType = PSRAM_WRAPPED_BURST,
95 .latency = PSRAM_WINBOND_6_CLOCKS_LATENCY,
96 .driveStrength = PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M,
97 };
98
99 PSram_Ctrl_Init(PSRAM0_ID, &default_psram_ctrl_cfg);
100 // PSram_Ctrl_Winbond_Reset(PSRAM0_ID);
101 PSram_Ctrl_Winbond_Write_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_CR0, &default_winbond_cfg);
102 }
103
board_psram_x8_init(void)104 static uint32_t board_psram_x8_init(void)
105 {
106 uint16_t reg_read = 0;
107
108 GLB_Set_PSRAMB_CLK_Sel(ENABLE, GLB_PSRAMB_EMI_WIFIPLL_320M, 0);
109
110 bflb_init_psram_gpio();
111
112 /* psram init*/
113 psram_winbond_default_init();
114 /* check psram work or not */
115 PSram_Ctrl_Winbond_Read_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_ID0, ®_read);
116 return reg_read;
117 }
118 #endif
119
120 /* This is the timer interrupt service routine. */
systick_isr(void)121 static void systick_isr(void)
122 {
123 rt_tick_increase();
124 }
125
rt_hw_board_init(void)126 void rt_hw_board_init(void)
127 {
128 #if defined (BSP_USING_BL61X_MODULE_DEFAULT)
129 bflb_flash_init();
130 #elif defined (BSP_USING_BL61X_MODULE_M0P)
131
132 #endif
133
134 system_clock_init();
135 peripheral_clock_init();
136 bflb_irq_initialize();
137
138 bflb_mtimer_config(HW_MTIMER_CLOCK / RT_TICK_PER_SECOND, systick_isr);
139
140 #ifdef RT_USING_HEAP
141 /* initialize memory system */
142 rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x size: %d\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END, RT_HW_HEAP_END - RT_HW_HEAP_BEGIN);
143 rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
144 #endif
145
146
147 /* UART driver initialization is open by default */
148 #ifdef RT_USING_SERIAL
149 rt_hw_uart_init();
150 #endif
151
152 #ifdef BSP_USING_PSRAM
153 board_psram_x8_init();
154 Tzc_Sec_PSRAMB_Access_Release();
155 #endif
156
157 /* Set the shell console output device */
158 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
159 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
160 #endif
161
162 #ifdef RT_USING_COMPONENTS_INIT
163 rt_components_board_init();
164 #endif
165 }
166
rt_hw_cpu_reset(void)167 void rt_hw_cpu_reset(void)
168 {
169 GLB_SW_POR_Reset();
170 }
171 MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
172