1 /* 2 * Copyright (c) 2022, sakumisu 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef CHERRYUSB_CONFIG_H 7 #define CHERRYUSB_CONFIG_H 8 9 /* ================ USB common Configuration ================ */ 10 11 #ifdef __RTTHREAD__ 12 #include <rtthread.h> 13 14 #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) 15 #else 16 #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) 17 #endif 18 19 #ifndef CONFIG_USB_DBG_LEVEL 20 #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO 21 #endif 22 23 /* Enable print with color */ 24 #define CONFIG_USB_PRINTF_COLOR_ENABLE 25 26 #define CONFIG_USB_DCACHE_ENABLE 27 28 /* data align size when use dma or use dcache */ 29 #ifdef CONFIG_USB_DCACHE_ENABLE 30 #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 31 #else 32 #define CONFIG_USB_ALIGN_SIZE 4 33 #endif 34 35 /* attribute data into no cache ram */ 36 #define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) 37 38 /* use usb_memcpy default for high performance but cost more flash memory. 39 * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. 40 */ 41 // #define CONFIG_USB_MEMCPY_DISABLE 42 43 /* ================= USB Device Stack Configuration ================ */ 44 45 /* Ep0 in and out transfer buffer */ 46 #ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN 47 #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 48 #endif 49 50 /* Setup packet log for debug */ 51 // #define CONFIG_USBDEV_SETUP_LOG_PRINT 52 53 /* Send ep0 in data from user buffer instead of copying into ep0 reqdata 54 * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE 55 */ 56 // #define CONFIG_USBDEV_EP0_INDATA_NO_COPY 57 58 /* Check if the input descriptor is correct */ 59 // #define CONFIG_USBDEV_DESC_CHECK 60 61 /* Enable test mode */ 62 // #define CONFIG_USBDEV_TEST_MODE 63 64 /* enable advance desc register api */ 65 #define CONFIG_USBDEV_ADVANCE_DESC 66 67 /* move ep0 setup handler from isr to thread */ 68 // #define CONFIG_USBDEV_EP0_THREAD 69 70 #ifndef CONFIG_USBDEV_EP0_PRIO 71 #define CONFIG_USBDEV_EP0_PRIO 4 72 #endif 73 74 #ifndef CONFIG_USBDEV_EP0_STACKSIZE 75 #define CONFIG_USBDEV_EP0_STACKSIZE 2048 76 #endif 77 78 #ifndef CONFIG_USBDEV_MSC_MAX_LUN 79 #define CONFIG_USBDEV_MSC_MAX_LUN 1 80 #endif 81 82 #ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE 83 #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 84 #endif 85 86 #ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING 87 #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" 88 #endif 89 90 #ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING 91 #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" 92 #endif 93 94 #ifndef CONFIG_USBDEV_MSC_VERSION_STRING 95 #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" 96 #endif 97 98 /* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ 99 // #define CONFIG_USBDEV_MSC_POLLING 100 101 /* move msc read & write from isr to thread */ 102 // #define CONFIG_USBDEV_MSC_THREAD 103 104 #ifndef CONFIG_USBDEV_MSC_PRIO 105 #define CONFIG_USBDEV_MSC_PRIO 4 106 #endif 107 108 #ifndef CONFIG_USBDEV_MSC_STACKSIZE 109 #define CONFIG_USBDEV_MSC_STACKSIZE 2048 110 #endif 111 112 #ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE 113 #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 114 #endif 115 116 #ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS 117 #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 118 #endif 119 120 #ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME 121 #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 122 #endif 123 124 #define CONFIG_USBDEV_MTP_THREAD 125 126 #ifndef CONFIG_USBDEV_MTP_PRIO 127 #define CONFIG_USBDEV_MTP_PRIO 4 128 #endif 129 130 #ifndef CONFIG_USBDEV_MTP_STACKSIZE 131 #define CONFIG_USBDEV_MTP_STACKSIZE 4096 132 #endif 133 134 #ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 135 #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 136 #endif 137 138 /* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ 139 #ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 140 #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 141 #endif 142 143 #ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID 144 #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff 145 #endif 146 147 #ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC 148 #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" 149 #endif 150 151 #define CONFIG_USBDEV_RNDIS_USING_LWIP 152 #define CONFIG_USBDEV_CDC_ECM_USING_LWIP 153 154 /* ================ USB HOST Stack Configuration ================== */ 155 156 #define CONFIG_USBHOST_MAX_RHPORTS 1 157 #define CONFIG_USBHOST_MAX_EXTHUBS 1 158 #define CONFIG_USBHOST_MAX_EHPORTS 4 159 #define CONFIG_USBHOST_MAX_INTERFACES 8 160 #define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 161 #define CONFIG_USBHOST_MAX_ENDPOINTS 4 162 163 #define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 164 #define CONFIG_USBHOST_MAX_HID_CLASS 4 165 #define CONFIG_USBHOST_MAX_MSC_CLASS 2 166 #define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 167 #define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 168 169 #define CONFIG_USBHOST_DEV_NAMELEN 16 170 171 #ifndef CONFIG_USBHOST_PSC_PRIO 172 #define CONFIG_USBHOST_PSC_PRIO 0 173 #endif 174 #ifndef CONFIG_USBHOST_PSC_STACKSIZE 175 #define CONFIG_USBHOST_PSC_STACKSIZE 2048 176 #endif 177 178 //#define CONFIG_USBHOST_GET_STRING_DESC 179 180 // #define CONFIG_USBHOST_MSOS_ENABLE 181 #ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE 182 #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 183 #endif 184 185 /* Ep0 max transfer buffer */ 186 #ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN 187 #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 188 #endif 189 190 #ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 191 #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 192 #endif 193 194 #ifndef CONFIG_USBHOST_MSC_TIMEOUT 195 #define CONFIG_USBHOST_MSC_TIMEOUT 5000 196 #endif 197 198 /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, 199 * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. 200 */ 201 #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE 202 #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) 203 #endif 204 205 /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ 206 #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE 207 #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) 208 #endif 209 210 /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, 211 * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. 212 */ 213 #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE 214 #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) 215 #endif 216 /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ 217 #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE 218 #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) 219 #endif 220 221 /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, 222 * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. 223 */ 224 #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE 225 #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) 226 #endif 227 /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ 228 #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE 229 #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) 230 #endif 231 232 /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, 233 * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. 234 */ 235 #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE 236 #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) 237 #endif 238 /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ 239 #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE 240 #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) 241 #endif 242 243 #define CONFIG_USBHOST_BLUETOOTH_HCI_H4 244 // #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG 245 246 #ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE 247 #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 248 #endif 249 #ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE 250 #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 251 #endif 252 253 /* ================ USB Device Port Configuration ================*/ 254 255 #ifndef CONFIG_USBDEV_MAX_BUS 256 #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip 257 #endif 258 259 #ifndef CONFIG_USBDEV_EP_NUM 260 #define CONFIG_USBDEV_EP_NUM 5 261 #endif 262 263 // #define CONFIG_USBDEV_SOF_ENABLE 264 265 /* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. */ 266 #define CONFIG_USB_HS 267 268 /* ---------------- FSDEV Configuration ---------------- */ 269 //#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference 270 271 /* ---------------- DWC2 Configuration ---------------- */ 272 /* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for 273 * status information) + (2 * number of OUT endpoints) + 1 for Global NAK 274 */ 275 // #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) 276 /* IN Endpoints Max packet Size / 4 */ 277 // #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) 278 // #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4) 279 // #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) 280 // #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) 281 // #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) 282 // #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) 283 // #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) 284 // #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) 285 // #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) 286 287 // #define CONFIG_USB_DWC2_DMA_ENABLE 288 289 /* ---------------- MUSB Configuration ---------------- */ 290 // #define CONFIG_USB_MUSB_SUNXI 291 292 /* ================ USB Host Port Configuration ==================*/ 293 #ifndef CONFIG_USBHOST_MAX_BUS 294 #define CONFIG_USBHOST_MAX_BUS 1 295 #endif 296 297 #ifndef CONFIG_USBHOST_PIPE_NUM 298 #define CONFIG_USBHOST_PIPE_NUM 10 299 #endif 300 301 /* ---------------- EHCI Configuration ---------------- */ 302 303 #define CONFIG_USB_EHCI_HCCR_OFFSET (0x0) 304 #define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 305 #define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM 306 #define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USB_EHCI_QH_NUM * 3) 307 #define CONFIG_USB_EHCI_ITD_NUM 4 308 #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE 309 // #define CONFIG_USB_EHCI_CONFIGFLAG 310 // #define CONFIG_USB_EHCI_ISO 311 // #define CONFIG_USB_EHCI_WITH_OHCI 312 // #define CONFIG_USB_EHCI_DESC_DCACHE_ENABLE 313 314 /* ---------------- OHCI Configuration ---------------- */ 315 #define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) 316 #define CONFIG_USB_OHCI_ED_NUM CONFIG_USBHOST_PIPE_NUM 317 #define CONFIG_USB_OHCI_TD_NUM 3 318 // #define CONFIG_USB_OHCI_DESC_DCACHE_ENABLE 319 320 /* ---------------- XHCI Configuration ---------------- */ 321 #define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) 322 323 /* ---------------- DWC2 Configuration ---------------- */ 324 /* largest non-periodic USB packet used / 4 */ 325 // #define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4) 326 /* largest periodic USB packet used / 4 */ 327 // #define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4) 328 /* 329 * (largest USB packet used / 4) + 1 for status information + 1 transfer complete + 330 * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario 331 */ 332 // #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE)) 333 334 /* ---------------- MUSB Configuration ---------------- */ 335 // #define CONFIG_USB_MUSB_SUNXI 336 337 #ifndef usb_phyaddr2ramaddr 338 #define usb_phyaddr2ramaddr(addr) (addr) 339 #endif 340 341 #ifndef usb_ramaddr2phyaddr 342 #define usb_ramaddr2phyaddr(addr) (addr) 343 #endif 344 345 #endif 346