1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2023/03/25 flyingcys first version
9 */
10 #include <rthw.h>
11 #include <rtthread.h>
12
13 #include "board.h"
14 #include "drv_uart.h"
15
system_clock_init(void)16 static void system_clock_init(void)
17 {
18 GLB_Set_System_CLK(GLB_DLL_XTAL_32M, GLB_SYS_CLK_DLL144M);
19 GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 71);
20 }
21
peripheral_clock_init(void)22 static void peripheral_clock_init(void)
23 {
24 PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
25 PERIPHERAL_CLOCK_SEC_ENABLE();
26 PERIPHERAL_CLOCK_DMA0_ENABLE();
27 PERIPHERAL_CLOCK_UART0_ENABLE();
28 PERIPHERAL_CLOCK_UART1_ENABLE();
29 PERIPHERAL_CLOCK_SPI0_ENABLE();
30 PERIPHERAL_CLOCK_I2C0_ENABLE();
31 PERIPHERAL_CLOCK_PWM0_ENABLE();
32 PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
33 PERIPHERAL_CLOCK_IR_ENABLE();
34 PERIPHERAL_CLOCK_I2S_ENABLE();
35 PERIPHERAL_CLOCK_USB_ENABLE();
36 GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM);
37
38 GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, 0);
39 GLB_Set_SPI_CLK(ENABLE, 0);
40 GLB_Set_I2C_CLK(ENABLE, 0);
41 GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 15);
42
43 GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
44 GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, 0x3E);
45
46 GLB_Set_USB_CLK(ENABLE);
47 }
48
49 #ifdef BSP_USING_PSRAM
50 struct spi_psram_cfg_type ap_memory1604 = {
51 .read_id_cmd = 0x9F,
52 .read_id_dmy_clk = 0,
53 .burst_toggle_cmd = 0xC0,
54 .reset_enable_cmd = 0x66,
55 .reset_cmd = 0x99,
56 .enter_quad_mode_cmd = 0x35,
57 .exit_quad_mode_cmd = 0xF5,
58 .read_reg_cmd = 0xB5,
59 .read_reg_dmy_clk = 1,
60 .write_reg_cmd = 0xB1,
61 .read_cmd = 0x03,
62 .read_dmy_clk = 0,
63 .f_read_cmd = 0x0B,
64 .f_read_dmy_clk = 1,
65 .f_read_quad_cmd = 0xEB,
66 .f_read_quad_dmy_clk = 3,
67 .write_cmd = 0x02,
68 .quad_write_cmd = 0x38,
69 .page_size = 512,
70 .ctrl_mode = PSRAM_SPI_CTRL_MODE,
71 .drive_strength = PSRAM_DRIVE_STRENGTH_50_OHMS,
72 .burst_length = PSRAM_BURST_LENGTH_512_BYTES,
73 };
74
75 struct sf_ctrl_cmds_cfg cmds_cfg = {
76 .cmds_core_en = 1,
77 .cmds_en = 1,
78 .burst_toggle_en = 1,
79 .cmds_wrap_mode = 0,
80 .cmds_wrap_len = SF_CTRL_WRAP_LEN_512,
81 };
82 struct sf_ctrl_psram_cfg psram_cfg = {
83 .owner = SF_CTRL_OWNER_SAHB,
84 .pad_sel = SF_CTRL_SEL_DUAL_CS_SF2,
85 .bank_sel = SF_CTRL_SEL_PSRAM,
86 .psram_rx_clk_invert_src = 1,
87 .psram_rx_clk_invert_sel = 0,
88 .psram_delay_src = 1,
89 .psram_clk_delay = 1,
90 };
91
92 #define BFLB_EXTFLASH_CS_GPIO GLB_GPIO_PIN_25
93 #define BFLB_EXTPSRAM_CLK_GPIO GLB_GPIO_PIN_27
94 #define BFLB_EXTPSRAM_CS_GPIO GLB_GPIO_PIN_17
95 #define BFLB_EXTPSRAM_DATA0_GPIO GLB_GPIO_PIN_28
96 #define BFLB_EXTPSRAM_DATA1_GPIO GLB_GPIO_PIN_24
97 #define BFLB_EXTPSRAM_DATA2_GPIO GLB_GPIO_PIN_23
98 #define BFLB_EXTPSRAM_DATA3_GPIO GLB_GPIO_PIN_26
99
psram_gpio_init(void)100 void ATTR_TCM_SECTION psram_gpio_init(void)
101 {
102 GLB_GPIO_Cfg_Type cfg;
103 uint8_t gpiopins[7];
104 uint8_t i = 0;
105
106 cfg.gpioMode = GPIO_MODE_AF;
107 cfg.pullType = GPIO_PULL_UP;
108 cfg.drive = 3;
109 cfg.smtCtrl = 1;
110 cfg.gpioFun = GPIO_FUN_FLASH_PSRAM;
111
112 gpiopins[0] = BFLB_EXTPSRAM_CLK_GPIO;
113 gpiopins[1] = BFLB_EXTPSRAM_CS_GPIO;
114 gpiopins[2] = BFLB_EXTPSRAM_DATA0_GPIO;
115 gpiopins[3] = BFLB_EXTPSRAM_DATA1_GPIO;
116 gpiopins[4] = BFLB_EXTPSRAM_DATA2_GPIO;
117 gpiopins[5] = BFLB_EXTPSRAM_DATA3_GPIO;
118 gpiopins[6] = BFLB_EXTFLASH_CS_GPIO;
119
120 for (i = 0; i < sizeof(gpiopins); i++) {
121 cfg.gpioPin = gpiopins[i];
122
123 if (i == 0 || i == 1 || i == 6) {
124 /*flash clk and cs is output*/
125 cfg.gpioMode = GPIO_MODE_OUTPUT;
126 } else {
127 /*data are bidir*/
128 cfg.gpioMode = GPIO_MODE_AF;
129 }
130
131 GLB_GPIO_Init(&cfg);
132 }
133 }
134
135 uint8_t psramId[8] = { 0 };
136
board_psram_init(void)137 void ATTR_TCM_SECTION board_psram_init(void)
138 {
139 psram_gpio_init();
140
141 bflb_psram_init(&ap_memory1604, &cmds_cfg, &psram_cfg);
142
143 bflb_psram_softwarereset(&ap_memory1604, ap_memory1604.ctrl_mode);
144
145 bflb_psram_readid(&ap_memory1604, psramId);
146 bflb_psram_cache_write_set(&ap_memory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE);
147 L1C_Cache_Enable_Set(L1C_WAY_DISABLE_NONE);
148 }
149 #endif
150
151 /* This is the timer interrupt service routine. */
systick_isr(void)152 static void systick_isr(void)
153 {
154 rt_tick_increase();
155 }
156
rt_hw_board_init(void)157 void rt_hw_board_init(void)
158 {
159 bflb_flash_init();
160
161 system_clock_init();
162 peripheral_clock_init();
163 bflb_irq_initialize();
164
165 bflb_mtimer_config(HW_MTIMER_CLOCK / RT_TICK_PER_SECOND, systick_isr);
166
167 #ifdef RT_USING_HEAP
168 /* initialize memory system */
169 rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
170 rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
171 #endif
172
173 /* UART driver initialization is open by default */
174 #ifdef RT_USING_SERIAL
175 rt_hw_uart_init();
176 #endif
177
178 #ifdef BSP_USING_PSRAM
179 board_psram_init();
180 #endif
181
182 /* Set the shell console output device */
183 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
184 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
185 #endif
186
187 #ifdef RT_USING_COMPONENTS_INIT
188 rt_components_board_init();
189 #endif
190 }
191
rt_hw_cpu_reset(void)192 void rt_hw_cpu_reset(void)
193 {
194 GLB_SW_POR_Reset();
195 }
196
197 MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
198