1 #include "fw_header.h" 2 3 __attribute__((section(".fw_header"))) struct bootheader_t fw_header = { 4 .magiccode = 0x504e4642, 5 .rivison = 0x00000001, 6 /*flash config */ 7 .flash_cfg.magiccode = 0x47464346, 8 .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ 9 .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ 10 .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ 11 .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ 12 .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ 13 .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ 14 .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ 15 .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ 16 .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ 17 .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ 18 .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ 19 .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ 20 .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ 21 .flash_cfg.cfg.mid = 0xff, /*!< Manufacturer ID */ 22 .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ 23 .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ 24 .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ 25 .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ 26 .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ 27 .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ 28 .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ 29 .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ 30 .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ 31 .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ 32 .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ 33 .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ 34 .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ 35 .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ 36 .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ 37 .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ 38 .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ 39 .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ 40 .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ 41 .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ 42 .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ 43 .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ 44 .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ 45 .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ 46 .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ 47 .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ 48 .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ 49 .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ 50 .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ 51 .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ 52 .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ 53 .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ 54 .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ 55 .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ 56 .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ 57 .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ 58 .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ 59 .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ 60 .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ 61 .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ 62 .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ 63 .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ 64 .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ 65 .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ 66 .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ 67 .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ 68 .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ 69 .flash_cfg.cfg.cReadMode = 0xa0, /*!< Config data for continuous read mode */ 70 .flash_cfg.cfg.cRExit = 0xff, /*!< Config data for exit continuous read mode */ 71 .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ 72 .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ 73 .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ 74 .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ 75 .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ 76 .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ 77 .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ 78 .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ 79 .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ 80 .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ 81 .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ 82 .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ 83 .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ 84 .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ 85 .flash_cfg.cfg.qeData = 0, /*!< QE set data */ 86 .flash_cfg.crc32 = 0xdeadbeef, 87 /* clock cfg */ 88 .clk_cfg.magiccode = 0x47464350, 89 .clk_cfg.cfg.xtal_type = 0x01, /*!< 0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M */ 90 .clk_cfg.cfg.pll_clk = 0x04, /*!< mcu_clk 0:RC32M, 1:XTAL, 2:PLL 57.6M, 3:PLL 96M, 4:PLL 144M */ 91 .clk_cfg.cfg.hclk_div = 0x00, 92 .clk_cfg.cfg.bclk_div = 0x01, 93 .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:144M, 1:XCLK(RC32M or XTAL), 2:57.6M, 3:72M, 4:BCLK, 5:96M */ 94 .clk_cfg.cfg.flash_clk_div = 0x00, 95 .clk_cfg.crc32 = 0xdeadbeef, 96 97 /* boot cfg */ 98 .boot_cfg.bval.sign = 0x0, /* [1: 0] for sign*/ 99 .boot_cfg.bval.encrypt_type = 0x0, /* [3: 2] for encrypt */ 100 .boot_cfg.bval.key_sel = 0x01, /* [5: 4] for key sel in boot interface*/ 101 .boot_cfg.bval.rsvd_7_6 = 0x0, /* [7: 6] for encrypt*/ 102 .boot_cfg.bval.no_segment = 0x1, /* [8] no segment info */ 103 .boot_cfg.bval.cache_select = 0x1, /* [9] for cache */ 104 .boot_cfg.bval.notload_in_bootrom = 0x0, /* [10] not load this img in bootrom */ 105 .boot_cfg.bval.aes_region_lock = 0x0, /* [11] aes region lock */ 106 .boot_cfg.bval.cache_way_disable = 0x0, /* [15: 12] cache way disable info*/ 107 .boot_cfg.bval.crc_ignore = 0x1, /* [16] ignore crc */ 108 .boot_cfg.bval.hash_ignore = 0x1, /* [17] hash crc */ 109 .boot_cfg.bval.halt_ap = 0x0, /* [18] halt ap */ 110 .boot_cfg.bval.boot2_enable = 0x00, /* [19] boot2 enable */ 111 .boot_cfg.bval.boot2_rollback = 0x00, /* [20] boot2 rollback */ 112 .boot_cfg.bval.rsvd_31_21 = 0x0, /* [31:21] rsvd */ 113 114 .img_segment_info.img_len = 0x00010000, /* image length or segment count */ 115 .rsvd0 = 0x00000000, 116 #ifdef BFLB_BOOT2 117 .img_start.flashoffset = 0x00002000, /* flash controller offset */ 118 #else 119 .img_start.flashoffset = 0x00001000, /* flash controller offset */ 120 #endif 121 .hash = { 0xdeadbeef }, /* hash of the image */ 122 123 .boot2_pt_table_0 = 0x1000, /* address of partition table 0 */ 124 .boot2_pt_table_1 = 0x2000, /* address of partition table 1 */ 125 .crc32 = 0xdeadbeef /* 4 */ 126 }; 127