1 #include "fw_header.h" 2 3 __attribute__((section(".fw_header"))) struct bootheader_t fw_header = { 4 .magiccode = 0x504e4642, 5 .rivison = 0x00000001, 6 /*flash config */ 7 .flash_cfg.magiccode = 0x47464346, 8 .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ 9 .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ 10 .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ 11 .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ 12 .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ 13 .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ 14 .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ 15 .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ 16 .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ 17 .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ 18 .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ 19 .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ 20 .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ 21 .flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */ 22 .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ 23 .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ 24 .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ 25 .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ 26 .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ 27 .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ 28 .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ 29 .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ 30 .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ 31 .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ 32 .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ 33 .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ 34 .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ 35 .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ 36 .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ 37 .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ 38 .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ 39 .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ 40 .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ 41 .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ 42 .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ 43 .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ 44 .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ 45 .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ 46 .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ 47 .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ 48 .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ 49 .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ 50 .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ 51 .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ 52 .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ 53 .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ 54 .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ 55 .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ 56 .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ 57 .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ 58 .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ 59 .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ 60 .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ 61 .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ 62 .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ 63 .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ 64 .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ 65 .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ 66 .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ 67 .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ 68 .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ 69 .flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */ 70 .flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */ 71 .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ 72 .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ 73 .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ 74 .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ 75 .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ 76 .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ 77 .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ 78 .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ 79 .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ 80 .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ 81 .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ 82 .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ 83 .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ 84 .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ 85 .flash_cfg.cfg.qeData = 0, /*!< QE set data */ 86 .flash_cfg.crc32 = 0xdeadbeef, 87 /* clock cfg */ 88 .clk_cfg.magiccode = 0x47464350, 89 .clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */ 90 .clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */ 91 .clk_cfg.cfg.mcu_clk_div = 0x00, 92 .clk_cfg.cfg.mcu_bclk_div = 0x00, 93 94 .clk_cfg.cfg.mcu_pbclk_div = 0x03, 95 .clk_cfg.cfg.lp_div = 0x01, 96 .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */ 97 .clk_cfg.cfg.dsp_clk_div = 0x00, 98 99 .clk_cfg.cfg.dsp_bclk_div = 0x01, 100 .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */ 101 .clk_cfg.cfg.dsp_pbclk_div = 0x00, 102 .clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */ 103 104 .clk_cfg.cfg.emi_clk_div = 0x01, 105 .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */ 106 .clk_cfg.cfg.flash_clk_div = 0x00, 107 .clk_cfg.cfg.wifipll_pu = 0x01, 108 109 .clk_cfg.cfg.aupll_pu = 0x01, 110 .clk_cfg.cfg.cpupll_pu = 0x01, 111 .clk_cfg.cfg.mipipll_pu = 0x01, 112 .clk_cfg.cfg.uhspll_pu = 0x01, 113 114 .clk_cfg.crc32 = 0xdeadbeef, 115 116 /* basic cfg */ 117 .basic_cfg.sign_type = 0x0, /* [1: 0] for sign */ 118 .basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */ 119 .basic_cfg.key_sel = 0x0, /* [5: 4] key slot */ 120 .basic_cfg.xts_mode = 0x0, /* [6] for xts mode */ 121 .basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */ 122 .basic_cfg.no_segment = 0x1, /* [8] no segment info */ 123 .basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */ 124 .basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */ 125 .basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */ 126 .basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */ 127 .basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */ 128 .basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */ 129 .basic_cfg.power_on_mm = 0x1, /* [18] power on mm */ 130 .basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */ 131 .basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */ 132 #if 0 133 # 0 : cmds bypass wrap commands to macro, original mode; 134 # 1 : cmds handle wrap commands, original mode; 135 # 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4; 136 # 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4 137 #endif 138 .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */ 139 #if 0 140 # 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32, 141 # 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096 142 #endif 143 .basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */ 144 .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */ 145 .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */ 146 .basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */ 147 148 #ifdef BFLB_BOOT2 149 .basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */ 150 #else 151 .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */ 152 #endif 153 .basic_cfg.aes_region_len = 0x00000000, /* aes region length */ 154 155 .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */ 156 .basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */ 157 158 /* cpu cfg */ 159 .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */ 160 .cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */ 161 .cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */ 162 .cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/ 163 .cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/ 164 .cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/ 165 .cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ 166 .cpu_cfg[0].rsvd = 0x0, 167 168 .cpu_cfg[0].cache_range_h = 0x00000000, 169 .cpu_cfg[0].cache_range_l = 0x00000000, 170 /* image_address_offset */ 171 .cpu_cfg[0].image_address_offset = 0x0, 172 .cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */ 173 .cpu_cfg[0].msp_val = 0x00000000, /* msp value */ 174 175 /* cpu cfg */ 176 .cpu_cfg[1].config_enable = 0x0, /* coinfig this cpu */ 177 .cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */ 178 .cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */ 179 .cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/ 180 .cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/ 181 .cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/ 182 .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ 183 .cpu_cfg[1].rsvd = 0x0, 184 185 .cpu_cfg[1].cache_range_h = 0x00000000, 186 .cpu_cfg[1].cache_range_l = 0x00000000, 187 /* image_address_offset */ 188 .cpu_cfg[1].image_address_offset = 0x0, 189 .cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */ 190 .cpu_cfg[1].msp_val = 0x00000000, /* msp value */ 191 192 /* address of partition table 0 */ /* 4 */ 193 .boot2_pt_table_0_rsvd = 0x00000000, 194 /* address of partition table 1 */ /* 4 */ 195 .boot2_pt_table_1_rsvd = 0x00000000, 196 197 /* address of flashcfg table list */ /* 4 */ 198 .flash_cfg_table_addr = 0x00000000, 199 /* flashcfg table list len */ /* 4 */ 200 .flash_cfg_table_len = 0x00000000, 201 202 .rsvd1[0] = 0x20000320, 203 .rsvd1[1] = 0x00000000, 204 .rsvd1[2] = 0x2000F038, 205 .rsvd1[3] = 0x18000000, 206 207 .crc32 = 0xdeadbeef /* 4 */ 208 }; 209