1 #ifndef __FW_HEADER_H__ 2 #define __FW_HEADER_H__ 3 4 #include "stdint.h" 5 #include "stdio.h" 6 7 struct __attribute__((packed, aligned(4))) spi_flash_cfg_t { 8 uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ 9 uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ 10 uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ 11 uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ 12 uint8_t resetEnCmd; /*!< Flash enable reset command */ 13 uint8_t resetCmd; /*!< Flash reset command */ 14 uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ 15 uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ 16 uint8_t jedecIdCmd; /*!< JEDEC ID command */ 17 uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ 18 uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ 19 uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ 20 uint8_t sectorSize; /*!< *1024bytes */ 21 uint8_t mid; /*!< Manufacturer ID */ 22 uint16_t pageSize; /*!< Page size */ 23 uint8_t chipEraseCmd; /*!< Chip erase cmd */ 24 uint8_t sectorEraseCmd; /*!< Sector erase command */ 25 uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ 26 uint8_t blk64EraseCmd; /*!< Block 64K erase command */ 27 uint8_t writeEnableCmd; /*!< Need before every erase or program */ 28 uint8_t pageProgramCmd; /*!< Page program cmd */ 29 uint8_t qpageProgramCmd; /*!< QIO page program cmd */ 30 uint8_t qppAddrMode; /*!< QIO page program address mode */ 31 uint8_t fastReadCmd; /*!< Fast read command */ 32 uint8_t frDmyClk; /*!< Fast read command dummy clock */ 33 uint8_t qpiFastReadCmd; /*!< QPI fast read command */ 34 uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ 35 uint8_t fastReadDoCmd; /*!< Fast read dual output command */ 36 uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ 37 uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ 38 uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ 39 uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ 40 uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ 41 uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ 42 uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ 43 uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ 44 uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ 45 uint8_t qpiPageProgramCmd; /*!< QPI program command */ 46 uint8_t writeVregEnableCmd; /*!< Enable write reg */ 47 uint8_t wrEnableIndex; /*!< Write enable register index */ 48 uint8_t qeIndex; /*!< Quad mode enable register index */ 49 uint8_t busyIndex; /*!< Busy status register index */ 50 uint8_t wrEnableBit; /*!< Write enable bit pos */ 51 uint8_t qeBit; /*!< Quad enable bit pos */ 52 uint8_t busyBit; /*!< Busy status bit pos */ 53 uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ 54 uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ 55 uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ 56 uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ 57 uint8_t releasePowerDown; /*!< Release power down command */ 58 uint8_t busyReadRegLen; /*!< Register length of contain busy status */ 59 uint8_t readRegCmd[4]; /*!< Read register command buffer */ 60 uint8_t writeRegCmd[4]; /*!< Write register command buffer */ 61 uint8_t enterQpi; /*!< Enter qpi command */ 62 uint8_t exitQpi; /*!< Exit qpi command */ 63 uint8_t cReadMode; /*!< Config data for continuous read mode */ 64 uint8_t cRExit; /*!< Config data for exit continuous read mode */ 65 uint8_t burstWrapCmd; /*!< Enable burst wrap command */ 66 uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ 67 uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ 68 uint8_t burstWrapData; /*!< Data to enable burst wrap */ 69 uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ 70 uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ 71 uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ 72 uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ 73 uint16_t timeEsector; /*!< 4K erase time */ 74 uint16_t timeE32k; /*!< 32K erase time */ 75 uint16_t timeE64k; /*!< 64K erase time */ 76 uint16_t timePagePgm; /*!< Page program time */ 77 uint16_t timeCe; /*!< Chip erase time in ms */ 78 uint8_t pdDelay; /*!< Release power down command delay time for wake up */ 79 uint8_t qeData; /*!< QE set data */ 80 }; 81 82 struct __attribute__((packed, aligned(4))) boot_flash_cfg_t { 83 uint32_t magiccode; 84 struct spi_flash_cfg_t cfg; 85 uint32_t crc32; 86 }; 87 88 struct __attribute__((packed, aligned(4))) sys_clk_cfg_t { 89 uint8_t xtal_type; 90 uint8_t mcu_clk; 91 uint8_t mcu_clk_div; 92 uint8_t mcu_bclk_div; 93 94 uint8_t mcu_pbclk_div; 95 uint8_t lp_div; 96 uint8_t dsp_clk; 97 uint8_t dsp_clk_div; 98 99 uint8_t dsp_bclk_div; 100 uint8_t dsp_pbclk; 101 uint8_t dsp_pbclk_div; 102 uint8_t emi_clk; 103 104 uint8_t emi_clk_div; 105 uint8_t flash_clk_type; 106 uint8_t flash_clk_div; 107 uint8_t wifipll_pu; 108 109 uint8_t aupll_pu; 110 uint8_t cpupll_pu; 111 uint8_t mipipll_pu; 112 uint8_t uhspll_pu; 113 }; 114 115 struct __attribute__((packed, aligned(4))) boot_clk_cfg_t { 116 uint32_t magiccode; 117 struct sys_clk_cfg_t cfg; 118 uint32_t crc32; 119 }; 120 121 struct __attribute__((packed, aligned(4))) boot_basic_cfg_t { 122 uint32_t sign_type : 2; /* [1: 0] for sign */ 123 uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ 124 uint32_t key_sel : 2; /* [5: 4] key slot */ 125 uint32_t xts_mode : 1; /* [6] for xts mode */ 126 uint32_t aes_region_lock : 1; /* [7] rsvd */ 127 uint32_t no_segment : 1; /* [8] no segment info */ 128 uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */ 129 uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */ 130 uint32_t cpu_master_id : 4; /* [14: 11] master id */ 131 uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ 132 uint32_t crc_ignore : 1; /* [16] ignore crc */ 133 uint32_t hash_ignore : 1; /* [17] hash ignore */ 134 uint32_t power_on_mm : 1; /* [18] power on mm */ 135 uint32_t em_sel : 3; /* [21: 19] em_sel */ 136 uint32_t cmds_en : 1; /* [22] command spliter enable */ 137 uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ 138 uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ 139 uint32_t icache_invalid : 1; /* [29] icache invalid */ 140 uint32_t dcache_invalid : 1; /* [30] dcache invalid */ 141 uint32_t rsvd_3 : 1; /* [31] rsvd_3 */ 142 143 uint32_t group_image_offset; /* flash controller offset */ 144 uint32_t aes_region_len; /* aes region length */ 145 146 uint32_t img_len_cnt; /* image length or segment count */ 147 uint32_t hash[32 / 4]; /* hash of the image */ 148 }; 149 150 struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t { 151 uint8_t config_enable; /* coinfig this cpu */ 152 uint8_t halt_cpu; /* halt this cpu */ 153 uint8_t cache_enable : 1; /* cache setting */ 154 uint8_t cache_wa : 1; /* cache setting */ 155 uint8_t cache_wb : 1; /* cache setting */ 156 uint8_t cache_wt : 1; /* cache setting */ 157 uint8_t cache_way_dis : 4; /* cache setting */ 158 uint8_t rsvd; 159 160 uint32_t cache_range_h; /* cache range high */ 161 uint32_t cache_range_l; /* cache range low */ 162 163 uint32_t image_address_offset; /* image_address_offset */ 164 uint32_t rsvd0; /* rsvd0 */ 165 uint32_t msp_val; /* msp value */ 166 }; 167 168 struct __attribute__((packed, aligned(4))) aesiv_cfg_t { 169 uint8_t aesiv[16]; 170 uint32_t crc32; 171 }; 172 173 struct __attribute__((packed, aligned(4))) pkey_cfg_t { 174 uint8_t eckeyx[32]; /* ec key in boot header */ 175 uint8_t eckeyy[32]; /* ec key in boot header */ 176 uint32_t crc32; 177 }; 178 179 struct __attribute__((packed, aligned(4))) sign_cfg_t { 180 uint32_t sig_len; 181 uint8_t signature[32]; 182 uint32_t crc32; 183 }; 184 185 struct __attribute__((packed, aligned(4))) bootheader_t { 186 uint32_t magiccode; /* 4 */ 187 uint32_t rivison; /* 4 */ 188 189 struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */ 190 struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */ 191 192 struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */ 193 194 struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */ 195 196 uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */ 197 uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */ 198 199 uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */ 200 uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */ 201 202 uint32_t rsvd0[8]; /* rsvd */ 203 uint32_t rsvd1[8]; /* rsvd */ 204 205 uint32_t rsvd3[5]; /* 20 */ 206 207 uint32_t crc32; /* 4 */ 208 }; 209 210 #define BFLB_FW_LENGTH_OFFSET 140 211 #define BFLB_FW_HASH_OFFSET 144 212 213 #endif 214