1 #ifndef _BFLB_DBI_H 2 #define _BFLB_DBI_H 3 4 #include "bflb_core.h" 5 6 /** @addtogroup LHAL 7 * @{ 8 */ 9 10 /** @addtogroup DBI 11 * @{ 12 */ 13 14 #if defined(BL616) 15 #define DBI_QSPI_SUPPORT 1 16 #define DBI_YUV_SUPPORT 1 17 #define DBI_WRITE_DATA_BYTE_MAX 256 18 #define DBI_READ_DATA_BYTE_MAX 8 19 #define SPI_FIFO_NUM_MAX 8 20 #elif defined(BL606P) || defined(BL808) 21 #define DBI_QSPI_SUPPORT 0 22 #define DBI_YUV_SUPPORT 0 23 #define DBI_WRITE_DATA_BYTE_MAX 4 24 #define DBI_READ_DATA_BYTE_MAX 4 25 #define SPI_FIFO_NUM_MAX 8 26 #else 27 #error "unknown device" 28 #endif 29 30 #define DBI_WRITE_PIXEL_CNT_MAX 0x00FFFFFF 31 32 /** @defgroup DBI_MODE dbi working mode definition 33 * @{ 34 */ 35 #define DBI_MODE_TYPE_B 0 /* mipi-dbi typeB 8-wire-data mode */ 36 #define DBI_MODE_TYPE_C_4_WIRE 1 /* mipi-dbi typeC 4-wire mode */ 37 #define DBI_MODE_TYPE_C_3_WIRE 2 /* mipi-dbi typeC 3-wire mode */ 38 #if (DBI_QSPI_SUPPORT) 39 #define DBI_MODE_EX_QSPI 3 /* Not the mipi standard. Extra support for QSPI mode */ 40 #endif 41 /** 42 * @} 43 */ 44 45 /** @defgroup DBI_PIXEL_INPUT_FORMAT dbi fifo input pixel format, the FIFO are filled in 32-bits width definition 46 * @{ 47 */ 48 #define DBI_PIXEL_INPUT_FORMAT_NBGR_8888 0 /* 32-bit/pixel, memory byte: [0]->pixel[0][R], [1]->pixel[0][G], [2]->pixel[0][B], [3]->invalid, [4]->pixel[1][R], ... */ 49 #define DBI_PIXEL_INPUT_FORMAT_NRGB_8888 1 /* 32-bit/pixel, memory byte: [0]->pixel[0][B], [1]->pixel[0][G], [2]->pixel[0][R], [3]->invalid, [4]->pixel[1][B], ... */ 50 #define DBI_PIXEL_INPUT_FORMAT_BGRN_8888 2 /* 32-bit/pixel, memory byte: [0]->invalid, [1]->pixel[0][R], [2]->pixel[0][G], [3]->pixel[0][B], [4]->invalid, [5]->pixel[1][R], ... */ 51 #define DBI_PIXEL_INPUT_FORMAT_RGBN_8888 3 /* 32-bit/pixel, memory byte: [0]->invalid, [1]->pixel[0][B], [2]->pixel[0][G], [3]->pixel[0][R], [4]->invalid, [5]->pixel[1][B], ... */ 52 #define DBI_PIXEL_INPUT_FORMAT_RGB_888 4 /* 24-bit/pixel, memory byte: [0]->pixel[0][R], [1]->pixel[0][G], [2]->pixel[0][B], [3]->pixel[1][R], [4]->pixel[1][G], ... */ 53 #define DBI_PIXEL_INPUT_FORMAT_BGR_888 5 /* 24-bit/pixel, memory byte: [0]->pixel[0][B], [1]->pixel[0][G], [2]->pixel[0][R], [3]->pixel[1][B], [4]->pixel[1][G], ... */ 54 #define DBI_PIXEL_INPUT_FORMAT_BGR_565 6 /* 16-bit/pixel, */ 55 #define DBI_PIXEL_INPUT_FORMAT_RGB_565 7 /* 16-bit/pixel, */ 56 /** 57 * @} 58 */ 59 60 /** @defgroup DBI_PIXEL_OUTPUT_FORMAT dbi output pixel format definition 61 * @{ 62 */ 63 #define DBI_PIXEL_OUTPUT_FORMAT_RGB_565 0 /* 16-bit/pixel */ 64 #define DBI_PIXEL_OUTPUT_FORMAT_RGB_888 1 /* 24-bit/pixel, Compatible with RGB666 format */ 65 /** 66 * @} 67 */ 68 69 /** @defgroup DBI_CLOCK_MODE dbi clock phase and polarity definition 70 * @{ 71 */ 72 #define DBI_CLOCK_MODE_0 0 /* CPOL=0 CHPHA=0 */ 73 #define DBI_CLOCK_MODE_1 1 /* CPOL=0 CHPHA=1 */ 74 #define DBI_CLOCK_MODE_2 2 /* CPOL=1 CHPHA=0 */ 75 #define DBI_CLOCK_MODE_3 3 /* CPOL=1 CHPHA=1 */ 76 /** 77 * @} 78 */ 79 80 /** @defgroup DBI_QSPI_WIRE_NUM dbi qspi wire num definition 81 * @{ 82 */ 83 #define DBI_QSPI_WIRE_NUM_1 0 /* 1-wire mode */ 84 #define DBI_QSPI_WIRE_NUM_4 1 /* 4-wire mode */ 85 /** 86 * @} 87 */ 88 89 /** @defgroup SPI_INTSTS dbi interrupt status definition 90 * @{ 91 */ 92 #define DBI_INTSTS_TC (1 << 0) 93 #define SPI_INTSTS_TX_FIFO (1 << 1) 94 #define SPI_INTSTS_FIFO_ERR (1 << 2) 95 /** 96 * @} 97 */ 98 99 /** @defgroup DBI_INTCLR dbi interrupt clear definition 100 * @{ 101 */ 102 #define DBI_INTCLR_TC (1 << 0) 103 /** 104 * @} 105 */ 106 107 /** @defgroup DBI_CMD dbi feature control cmd definition 108 * @{ 109 */ 110 #define DBI_CMD_CLEAR_TX_FIFO (0x01) 111 #define DBI_CMD_GET_TX_FIFO_CNT (0x02) 112 #define DBI_CMD_MASK_CMD_PHASE (0x03) 113 #define DBI_CMD_CS_CONTINUE (0x04) 114 #define DBI_CMD_SET_DUMMY_CNT (0x05) 115 #define DBI_CMD_GET_SIZE_OF_PIXEL_CNT (0x06) 116 #define DBI_CMD_INPUT_PIXEL_FORMAT (0x07) 117 #define DBI_CMD_OUTPUT_PIXEL_FORMAT (0x08) 118 #if (DBI_QSPI_SUPPORT) 119 #define DBI_CMD_YUV_TO_RGB_ENABLE (0x10) 120 #endif 121 122 /** 123 * @} 124 */ 125 126 /** 127 * @} 128 */ 129 130 /** 131 * @} 132 */ 133 134 /** 135 * @brief DBI configuration structure 136 * 137 * @param dbi_mode DBI working mode, use @ref DBI_MODE 138 * @param pixel_input_format DBI input pixel_format, use @ref DBI_PIXEL_INPUT_FORMAT 139 * @param pixel_output_format DBI output pixel_format, use @ref DBI_PIXEL_OUTPUT_FORMAT 140 * @param clk_mode DBI clock phase and polarity, use @ref DBI_CLOCK_MODE 141 * @param clk_freq_hz DBI clock frequency 142 * @param tx_fifo_threshold DBI tx fifo threshold, should be less than 16 143 * @param cmd_wire_mode DBI qspi mode, number of wire in the command phase, use @ref DBI_QSPI_WIRE_NUM 144 * @param addr_wire_mode DBI qspi mode, number of wire in the address phase, use @ref DBI_QSPI_WIRE_NUM 145 * @param data_wire_mode DBI qspi mode, number of wire in the data phase, use @ref DBI_QSPI_WIRE_NUM 146 */ 147 struct bflb_dbi_config_s { 148 uint8_t dbi_mode; 149 uint8_t pixel_input_format; 150 uint8_t pixel_output_format; 151 uint8_t clk_mode; 152 uint32_t clk_freq_hz; 153 uint8_t tx_fifo_threshold; 154 #if (DBI_QSPI_SUPPORT) 155 uint8_t cmd_wire_mode; 156 uint8_t addr_wire_mode; 157 uint8_t data_wire_mode; 158 #endif 159 }; 160 161 #ifdef __cplusplus 162 extern "C" { 163 #endif 164 165 /** 166 * @brief Initialize dbi. 167 * 168 * @param [in] dev device handle 169 * @param [in] config pointer to save dbi config 170 */ 171 void bflb_dbi_init(struct bflb_device_s *dev, const struct bflb_dbi_config_s *config); 172 173 /** 174 * @brief Deinitialize dbi. 175 * 176 * @param [in] dev device handle 177 */ 178 void bflb_dbi_deinit(struct bflb_device_s *dev); 179 180 #if DBI_QSPI_SUPPORT 181 /** 182 * @brief Set the address value and address length of the QSPI 183 * 184 * @param [in] dev device handle 185 * @param [in] addr_byte_size address size(byte), range 1 ~ 4 186 * @param [in] addr_val address value: [0:7]->addr[0], [8:15]->addr[1], [16:23]->addr[2], [24:31]->addr[3]. 187 */ 188 void bflb_dbi_qspi_set_addr(struct bflb_device_s *dev, uint8_t addr_byte_size, uint32_t addr_val); 189 190 #endif 191 192 /** 193 * @brief Send cmd with pixel data, send cmd -> send address(only QSPI mode) -> send parameter_data. 194 * 195 * @param [in] dev device handle 196 * @param [in] cmd command 197 * @param [in] data_len Parameter length (byte), The maximum is DBI_WRITE_DATA_BYTE_MAX 198 * @param [in] data_buff Parameter buffer, Cannot be null 199 * @return 200 */ 201 int bflb_dbi_send_cmd_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff); 202 203 /** 204 * @brief To read the data after sending the command, send cmd -> send address(only QSPI mode) -> read parameter_data. 205 * 206 * @param [in] dev device handle 207 * @param [in] cmd command 208 * @param [in] data_len Length of data to be read (byte), The maximum is DBI_READ_DATA_BYTE_MAX 209 * @param [in] data_buff Buff of data to be read, discard data if null 210 * @return 211 */ 212 int bflb_dbi_send_cmd_read_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff); 213 214 /** 215 * @brief Send cmd with pixel data, send cmd -> send address(only QSPI mode) -> send pixel_data, 216 * 217 * @param [in] dev device handle 218 * @param [in] cmd command 219 * @param [in] pixel_cnt Number of pixels,The maximum is DBI_WRITE_PIXEL_CNT_MAX 220 * @param [in] pixel_buff Pixels buffer, NULL when using DMA, in which case data needs to be transferred by DMA later, and wait for the transfer to complete 221 * @return 222 */ 223 int bflb_dbi_send_cmd_pixel(struct bflb_device_s *dev, uint8_t cmd, uint32_t pixel_cnt, void *pixel_buff); 224 225 /** 226 * @brief Enable dbi tx dma. 227 * 228 * @param [in] dev device handle 229 * @param [in] enable true means enable, otherwise disable. 230 */ 231 void bflb_dbi_link_txdma(struct bflb_device_s *dev, bool enable); 232 233 /** 234 * @brief Enable or disable dbi rx fifo threhold interrupt. 235 * 236 * @param [in] dev device handle 237 * @param [in] mask true means disable, false means enable 238 */ 239 void bflb_dbi_txint_mask(struct bflb_device_s *dev, bool mask); 240 241 /** 242 * @brief Enable or disable dbi transfer completion interrupt. 243 * 244 * @param [in] dev device handle 245 * @param [in] mask true means disable, false means enable 246 */ 247 void bflb_dbi_tcint_mask(struct bflb_device_s *dev, bool mask); 248 249 /** 250 * @brief Enable or disable dbi error interrupt. 251 * 252 * @param [in] dev device handle 253 * @param [in] mask true means disable, false means enable 254 */ 255 void bflb_dbi_errint_mask(struct bflb_device_s *dev, bool mask); 256 257 /** 258 * @brief Get dbi interrupt status. 259 * 260 * @param [in] dev device handle 261 * @return interrupt status, use @ref DBI_INTSTS 262 */ 263 uint32_t bflb_dbi_get_intstatus(struct bflb_device_s *dev); 264 265 /** 266 * @brief Clear dbi interrupt status. 267 * 268 * @param [in] dev device handle 269 * @param [in] int_clear clear value, use @ref SPI_INTCLR 270 */ 271 void bflb_dbi_int_clear(struct bflb_device_s *dev, uint32_t int_clear); 272 273 /** 274 * @brief Control dbi feature. 275 * 276 * @param [in] dev device handle 277 * @param [in] cmd feature command, use @ref DBI_CMD 278 * @param [in] arg user data 279 * @return A negated errno value on failure. 280 */ 281 int bflb_dbi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); 282 283 #ifdef __cplusplus 284 } 285 #endif 286 287 /** 288 * @} 289 */ 290 291 /** 292 * @} 293 */ 294 295 #endif 296