1 /* 2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 /****************************************************************************** 17 * @file ck_dmac.h 18 * @brief header file for DMAC Driver 19 * @version V1.0 20 * @date 02. June 2017 21 ******************************************************************************/ 22 #ifndef __CK_DMA_H 23 #define __CK_DMA_H 24 #include <stdio.h> 25 #include "soc.h" 26 27 #define CK_DMA_MAXCHANNEL 2 28 #define CK_DMA_INT_EN 1 29 #define CK_DMA_CH_EN 1 30 #define CK_DMA_TFR 0x0002 31 #define CK_DMA_ERR 0x0001 32 #define CK_DMA_INTC 0x03 33 #define CK_DMA_MASK 0x03 34 35 typedef enum { 36 DMA_ADDR_INCREMENT = 0, 37 DMA_ADDR_DECREMENT = 1, 38 DMA_ADDR_NOCHANGE = 2 39 } enum_addr_state_e; 40 41 typedef enum { 42 DMA_DATAWIDTH_SIZE8 = 1, 43 DMA_DATAWIDTH_SIZE16 = 2, 44 DMA_DATAWIDTH_SIZE32 = 4 45 } dma_datawidth_e; 46 47 typedef enum { 48 DMA_HANDSHAKING_HARDWARE = 0, 49 DMA_HANDSHAKING_SOFTWARE = 1, 50 } dma_handshaking_select_e; 51 52 typedef enum { 53 DMA_PRIORITY0 = 0, 54 DMA_PRIORITY1 = 1, 55 DMA_PRIOTITY2 = 2, 56 DMA_PRIOTITY3 = 3 57 } dma_priority_t; 58 59 typedef struct { 60 __IOM uint32_t SAR; /* offset: 0x00 (R/W) Channel Source Address Register */ 61 __IOM uint32_t DAR; /* offset: 0x04 (R/W) Channel Destination Address Register */ 62 __IOM uint32_t CHCTRLA; /* offset: 0x08 (R/W) Channel Control Register A */ 63 __IOM uint32_t CHCTRLB; /* offset: 0x0C (R/W) Channel Control Register B */ 64 __IOM uint8_t CHINTM:2; /* offset: 0x10 (R/W) Channel Interrupt Mask Register */ 65 uint8_t RESERVED0[3]; 66 __IM uint8_t CHINTS:2; /* offset: 0x14 (R/ ) Channel Interrupt Status Register */ 67 uint8_t RESERVED1[3]; 68 __IOM uint8_t CHINTC:2; /* offset: 0x18 (R/W) Channel Interrupt Clear Register */ 69 uint8_t RESERVED2[3]; 70 __IOM uint8_t CHSREQ:1; /* offset: 0x1C (R/W) Channel Software Request Register */ 71 uint8_t RESERVED3[3]; 72 __IOM uint8_t CHEN:1; /* offset: 0x20 (R/W) Channel Enable Register */ 73 uint8_t RESERVED4[3]; 74 } ck_dma_reg_t; 75 #endif /* __CK_DMA_H */ 76