1 /*
2  * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *   http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 /******************************************************************************
18  * @file     dw_gpio.h
19  * @brief    header file for GPIO Driver
20  * @version  V1.0
21  * @date     02. June 2017
22  ******************************************************************************/
23 #ifndef _DW_GPIO_H_
24 #define _DW_GPIO_H_
25 
26 #include "drv_gpio.h"
27 #include "soc.h"
28 
29 
30 typedef struct {
31     __IOM uint32_t SWPORT_DR;                     /* Offset: 0x000 (W/R)  PortA data register */
32     __IOM uint32_t SWPORT_DDR;                    /* Offset: 0x004 (W/R)  PortA data direction register */
33     __IOM uint32_t PORT_CTL;                      /* Offset: 0x008 (W/R)  PortA source register */
34 
35 } dw_gpio_reg_t;
36 
37 typedef struct {
38     __IOM uint32_t INTEN;                         /* Offset: 0x000 (W/R)  Interrupt enable register */
39     __IOM uint32_t INTMASK;                       /* Offset: 0x004 (W/R)  Interrupt mask register */
40     __IOM uint32_t INTTYPE_LEVEL;                 /* Offset: 0x008 (W/R)  Interrupt level register */
41     __IOM uint32_t INT_POLARITY;                  /* Offset: 0x00c (W/R)  Interrupt polarity register */
42     __IM  uint32_t INTSTATUS;                     /* Offset: 0x010 (R)    Interrupt status of Port */
43     __IM  uint32_t RAWINTSTATUS;                  /* Offset: 0x014 (W/R)  Raw interrupt status of Port */
44     __IOM uint32_t revreg1;                       /* Offset: 0x018 (W/R)  Reserve register */
45     __OM  uint32_t PORTA_EOI;                     /* Offset: 0x01c (W/R)  Port clear interrupt register */
46     __IM  uint32_t EXT_PORTA;                     /* Offset: 0x020 (W/R)  PortA external port register */
47     __IM  uint32_t EXT_PORTB;                     /* Offset: 0x024 (W/R)  PortB external port register */
48     __IOM uint32_t revreg2[2];                    /* Offset: 0x028 (W/R)  Reserve register */
49     __IOM uint32_t LS_SYNC;                       /* Offset: 0x030 (W/R)  Level-sensitive synchronization enable register */
50 
51 } dw_gpio_control_reg_t;
52 
53 #endif
54 
55