1 /* 2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 /****************************************************************************** 17 * @file ck_sha.h 18 * @brief header file for sha driver 19 * @version V1.0 20 * @date 02. June 2017 21 ******************************************************************************/ 22 #ifndef _CK_SHA_H_ 23 #define _CK_SHA_H_ 24 25 #include <stdio.h> 26 #include "drv_sha.h" 27 #include "soc.h" 28 29 #define SHA_INIT_OFFSET 3 30 #define SHA_INT_ENABLE_OFFSET 4 31 #define SHA_ENDIAN_OFFSET 5 32 #define SHA_CAL_OFFSET 6 33 typedef struct { 34 __IOM uint32_t SHA_CON; /* Offset: 0x000 (R/W) Control register */ 35 __IOM uint32_t SHA_INTSTATE; /* Offset: 0x004 (R/W) Instatus register */ 36 __IOM uint32_t SHA_H0L; /* Offset: 0x008 (R/W) H0L register */ 37 __IOM uint32_t SHA_H1L; /* Offset: 0x00c (R/W) H1L register */ 38 __IOM uint32_t SHA_H2L; /* Offset: 0x010 (R/W) H2L register */ 39 __IOM uint32_t SHA_H3L; /* Offset: 0x014 (R/W) H3L register */ 40 __IOM uint32_t SHA_H4L; /* Offset: 0x018 (R/W) H4L register */ 41 __IOM uint32_t SHA_H5L; /* Offset: 0x01c (R/W) H5L register */ 42 __IOM uint32_t SHA_H6L; /* Offset: 0x020 (R/W) H6L register */ 43 __IOM uint32_t SHA_H7L; /* Offset: 0x024 (R/W) H7L register */ 44 __IOM uint32_t SHA_H0H; /* Offset: 0x028 (R/W) H0H register */ 45 __IOM uint32_t SHA_H1H; /* Offset: 0x02c (R/W) H1H register */ 46 __IOM uint32_t SHA_H2H; /* Offset: 0x030 (R/W) H2H register */ 47 __IOM uint32_t SHA_H3H; /* Offset: 0x034 (R/W) H3H register */ 48 __IOM uint32_t SHA_H4H; /* Offset: 0x038 (R/W) H4H register */ 49 __IOM uint32_t SHA_H5H; /* Offset: 0x03c (R/W) H5H register */ 50 __IOM uint32_t SHA_H6H; /* Offset: 0x040 (R/W) H6H register */ 51 __IOM uint32_t SHA_H7H; /* Offset: 0x044 (R/W) H7H register */ 52 __IOM uint32_t SHA_DATA1; /* Offset: 0x048 (R/W) DATA1 register */ 53 uint32_t REV[15]; 54 __IOM uint32_t SHA_DATA2; /* Offset: 0x088 (R/W) DATA2 register */ 55 } ck_sha_reg_t; 56 #endif 57 58 typedef enum { 59 SHA_STATUS_START_END = 0, /* the one time count mode */ 60 SHA_STATUS_START = 1, /* the first time of the cal */ 61 SHA_STATUS_CONTINUE = 2, /* the middle stage of the cal */ 62 SHA_STATUS_END = 3 /* the last time of the cal*/ 63 } enum_sha_status; 64