1 /* 2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 /****************************************************************************** 17 * @file dw_spi.h 18 * @brief header file for spi driver 19 * @version V1.0 20 * @date 02. June 2017 21 ******************************************************************************/ 22 #ifndef __DW_SPI_H 23 #define __DW_SPI_H 24 25 #include <stdio.h> 26 #include "soc.h" 27 28 /* 29 * SPI register bit definitions 30 */ 31 #define DW_SPI_ENABLE 0x01 32 #define DW_SPI_DISABLE 0x00 33 #define DW_SPI_TMOD_BIT8 0x0100 34 #define DW_SPI_TMOD_BIT9 0x0200 35 #define DW_SPI_POLARITY 0x80 36 #define DW_SPI_PHASE 0x40 37 #define DW_SPI_BUSY 0x01 38 #define DW_SPI_TFE 0x04 39 #define DW_SPI_RFNE 0x08 40 #define DW_SPI_INT_EN 0x19 41 #define DW_SPI_RINT_EN 0x3e 42 #define DW_SPI_TINT_EN 0x3f 43 #define DW_SPI_INT_DISABLE 0x00 44 #define DW_SPI_INT_MASK_RX 0x27 45 #define DW_SPI_INT_MASKTX 0x3e 46 #define DW_SPI_RDMAE 0x1 47 #define DW_SPI_TDMAE 0x2 48 #define DW_SPI_TXFIFO_LV 0x0 49 #define DW_SPI_RXFIFO_LV 0x1d 50 #define DW_SPI_RXFIFO_NOT_EMPTY 0x08 51 #define DW_SPI_START_RX 0x0 52 #define DW_SPI_FIFO_MAX_LV 0x20 53 #define DW_SPI_FIFO_OVER_LV 0x18 54 #define DW_SPI_RXFIFO_OVERFLOW 0x08 55 #define DW_SPI_RXFIFO_FULL 0x10 56 #define DW_SPI_TXFIFO_EMPTY 0x01 57 #define SPI_CS_SELECTED 0x0 58 #define DW_SPI_IMR_TXEIM 0x01 /* Transmit FIFO Empty Interrupt Mask */ 59 #define DW_SPI_IMR_RXFIM 0x10 /* Receive FIFO Full Interrupt Mask */ 60 61 62 /* some infoermationgs of SPI for special MCU */ 63 #define DW_SPI_DEFAULT_BAUDR 10000000 /* 10M */ 64 #define DW_SPI_MAXID 0x1 65 66 #define SPI_INITIALIZED ((uint8_t)(1U)) // SPI initalized 67 #define SPI_POWERED ((uint8_t)(1U<< 1)) // SPI powered on 68 #define SPI_CONFIGURED ((uint8_t)(1U << 2)) // SPI configured 69 #define SPI_DATA_LOST ((uint8_t)(1U << 3)) // SPI data lost occurred 70 #define SPI_MODE_FAULT ((uint8_t)(1U << 4)) // SPI mode fault occurred 71 72 73 typedef enum { 74 DWENUM_SPI_DMACR_RXE = 0, 75 DWENUM_SPI_DMACR_TXE = 1, 76 } DWENUM_SPI_DMACR; 77 78 79 typedef enum { 80 DWENUM_SPI_TXRX = 0, 81 DWENUM_SPI_TX = 1, 82 DWENUM_SPI_RX = 2, 83 DWENUM_SPI_EERX = 3 84 } DWENUM_SPI_MODE; 85 86 typedef enum { 87 DWENUM_SPI_CLOCK_POLARITY_LOW = 0, 88 DWENUM_SPI_CLOCK_POLARITY_HIGH = 1 89 } DWENUM_SPI_POLARITY; 90 91 typedef enum { 92 DWENUM_SPI_CLOCK_PHASE_MIDDLE = 0, 93 DWENUM_SPI_CLOCK_PHASE_START = 1 94 } DWENUM_SPI_PHASE; 95 96 typedef enum { 97 DWENUM_SPI_DATASIZE_4 = 3, 98 DWENUM_SPI_DATASIZE_5 = 4, 99 DWENUM_SPI_DATASIZE_6 = 5, 100 DWENUM_SPI_DATASIZE_7 = 6, 101 DWENUM_SPI_DATASIZE_8 = 7, 102 DWENUM_SPI_DATASIZE_9 = 8, 103 DWENUM_SPI_DATASIZE_10 = 9, 104 DWENUM_SPI_DATASIZE_11 = 10, 105 DWENUM_SPI_DATASIZE_12 = 11, 106 DWENUM_SPI_DATASIZE_13 = 12, 107 DWENUM_SPI_DATASIZE_14 = 13, 108 DWENUM_SPI_DATASIZE_15 = 14, 109 DWENUM_SPI_DATASIZE_16 = 15 110 } DWENUM_SPI_DATAWIDTH; 111 112 typedef enum { 113 DWENUM_SPI_CS0 = 1, 114 DWENUM_SPI_CS1 = 2 115 } DWENUM_SPI_SLAVE; 116 117 typedef struct { 118 __IOM uint16_t CTRLR0; /* Offset: 0x000 (R/W) Control register 0 */ 119 uint16_t RESERVED0; 120 __IOM uint16_t CTRLR1; /* Offset: 0x004 (R/W) Control register 1 */ 121 uint16_t RESERVED1; 122 __IOM uint8_t SPIENR; /* Offset: 0x008 (R/W) SSI enable regiseter */ 123 uint8_t RESERVED2[7]; 124 __IOM uint32_t SER; /* Offset: 0x010 (R/W) Slave enable register */ 125 __IOM uint16_t BAUDR; /* Offset: 0x014 (R/W) Baud rate select */ 126 uint16_t RESERVED3; 127 __IOM uint32_t TXFTLR; /* Offset: 0x018 (R/W) Transmit FIFO Threshold Level */ 128 __IOM uint32_t RXFTLR; /* Offset: 0x01c (R/W) Receive FIFO Threshold Level */ 129 __IOM uint32_t TXFLR; /* Offset: 0x020 (R/W) Transmit FIFO Level register */ 130 __IOM uint32_t RXFLR; /* Offset: 0x024 (R/W) Receive FIFO Level Register */ 131 __IOM uint8_t SR; /* Offset: 0x028 (R/W) status register */ 132 uint8_t RESERVED4[3]; 133 __IOM uint32_t IMR; /* Offset: 0x02C (R/W) Interrupt Mask Register */ 134 __IM uint32_t ISR; /* Offset: 0x030 (R/W) interrupt status register */ 135 __IM uint32_t RISR; /* Offset: 0x034 (R/W) Raw Interrupt Status Register */ 136 __IM uint8_t TXOICR; /* Offset: 0x038 (R/W) Transmit FIFO Overflow Interrupt Clear Register */ 137 uint8_t RESERVED5[3]; 138 __IM uint8_t RXOICR; /* Offset: 0x03C (R/W) Receive FIFO Overflow Interrupt Clear Register*/ 139 uint8_t RESERVED6[3]; 140 __IM uint8_t RXUICR; /* Offset: 0x040 (R/W) Receive FIFO Underflow Interrupt Clear Register */ 141 uint8_t RESERVED7[3]; 142 __IM uint8_t MSTICR; /* Offset: 0x044 (R/W) Multi-Master Interrupt Clear Register */ 143 uint8_t RESERVED8[3]; 144 __IM uint8_t ICR; /* Offset: 0x048 (R/W) Interrupt Clear Register */ 145 uint8_t RESERVED9[3]; 146 __IOM uint8_t DMACR; /* Offset: 0x04C (R/W) DMA Control Register */ 147 uint8_t RESERVED10[3]; 148 __IOM uint8_t DMATDLR; /* Offset: 0x050 (R/W) DMA Transmoit Data Level */ 149 uint8_t RESERVED11[3]; 150 __IOM uint8_t DMARDLR; /* Offset: 0x054 (R/W) DMA Receive Data Level */ 151 uint8_t RESERVED12[3]; 152 __IM uint32_t IDR; /* Offset: 0x058 (R/W) identification register */ 153 uint32_t RESERVED13; 154 __IOM uint16_t DR; /* Offset: 0x060 (R/W) Data Register */ 155 uint16_t RESERVED14[17]; 156 __IOM uint8_t WR; /* Offset: 0x0A0 (R/W) SPI is Master or Slave Select Register */ 157 } dw_spi_reg_t; 158 159 #endif /* __DW_SPI_H */ 160