1/*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date           Author       Notes
8 * 2017-01-01     Urey      first version
9 */
10
11
12#undef  VIC_TSPR
13#define VIC_TSPR                    0xE000EC10
14
15#ifndef CONFIG_SEPARATE_IRQ_SP
16#define CONFIG_SEPARATE_IRQ_SP      1
17#endif
18
19#ifndef CONFIG_ARCH_INTERRUPTSTACK
20#define CONFIG_ARCH_INTERRUPTSTACK  1024
21#endif
22
23.import SysTick_Handler
24.import PendSV_Handler
25
26    .section .vectors
27    .align 10
28    .globl  __Vectors
29    .type   __Vectors, @object
30__Vectors:
31    .long   Reset_Handler         /* 0: Reset Handler */
32
33    .rept   15
34    .long   Default_Handler       /* 60 0x40 */
35    .endr                         /* 64 0x40 */
36
37    .long   Default_Handler       /* 64 0x44 */
38
39    .rept   5
40    .long   Default_Handler       /* 88 0x58 */
41    .endr                         /* 92 0x5C */
42
43    .long   PendSV_Handler        /* 92 0x5C */
44
45    .rept   9
46    .long   Default_Handler       /* 128 0x80 */
47    .endr
48
49    /* External interrupts */
50    .long   GPIOA_IRQHandler         /*  32#  0:  GPIOA           */ /*128  0x80 */
51    .long   SysTick_Handler          /*  1:  System Tick     */
52    .long   TIMA0_IRQHandler         /*  2:  TimerA0         */
53    .long   TIMA1_IRQHandler         /*  3:  TimerA1         */
54    .long   Default_Handler
55    .long   WDT_IRQHandler           /*  5:  WDT            */
56    .long   USART0_IRQHandler        /*  6:  UART0          */
57    .long   USART1_IRQHandler        /*  0x27 39 7:  UART1          */
58    .long   USART2_IRQHandler        /*  8:  UART2          */
59    .long   I2C0_IRQHandler          /*  9:  I2C0           */
60    .long   I2C1_IRQHandler          /*  10: I2C1           */
61    .long   SPI1_IRQHandler          /*  11: SPI1           */
62    .long   SPI0_IRQHandler          /*  12: SPI0           */
63    .long   RTC_IRQHandler           /*  13: RTC            */
64    .long   Default_Handler
65    .long   Default_Handler
66    .long   Default_Handler
67    .long   DMAC_IRQHandler          /*  17: DMAC           */
68    .long   Default_Handler
69    .long   PWM_IRQHandler           /*  19: PWM            */
70    .long   Default_Handler
71    .long   USART3_IRQHandler        /*  21: UART3          */
72    .long   Default_Handler
73    .long   TIMB0_IRQHandler         /*  23: TimerB0        */
74    .long   TIMB1_IRQHandler         /*  24: TimerB1        */
75    .long   Default_Handler
76    .long   AES_IRQHandler           /*  26:  AES            */
77    .long   GPIOB_IRQHandler         /*  27:  GPIOB          */
78    .long   Default_Handler
79    .long   SHA_IRQHandler           /*  29:  SHA            */
80
81    .size   __Vectors, . - __Vectors
82
83    .text
84    .align  1
85_start:
86    .text
87    .align  1
88    .globl  Reset_Handler
89    .type   Reset_Handler, %function
90Reset_Handler:
91    /* under normal circumstances,  it should not be opened */
92
93#ifndef CONFIG_SYSTEM_SECURE
94    lrw     r0, 0x80000000
95    mtcr    r0, psr
96#endif
97
98/* Initialize the normal stack pointer from the linker definition. */
99    lrw     a1, __StackTop
100    mov     sp, a1
101
102/*
103 *  The ranges of copy from/to are specified by following symbols
104 *    __etext: LMA of start of the section to copy from. Usually end of text
105 *    __data_start__: VMA of start of the section to copy to
106 *    __data_end__: VMA of end of the section to copy to
107 *
108 *  All addresses must be aligned to 4 bytes boundary.
109 */
110    lrw     r1, __erodata
111    lrw     r2, __data_start__
112    lrw     r3, __data_end__
113
114    subu    r3, r2
115    cmpnei  r3, 0
116    bf      .L_loop0_done
117
118.L_loop0:
119    ldw     r0, (r1, 0)
120    stw     r0, (r2, 0)
121    addi    r1, 4
122    addi    r2, 4
123    subi    r3, 4
124    cmpnei  r3, 0
125    bt      .L_loop0
126
127.L_loop0_done:
128
129/*
130 *  The BSS section is specified by following symbols
131 *    __bss_start__: start of the BSS section.
132 *    __bss_end__: end of the BSS section.
133 *
134 *  Both addresses must be aligned to 4 bytes boundary.
135 */
136    lrw     r1, __bss_start__
137    lrw     r2, __bss_end__
138
139    movi    r0, 0
140
141    subu    r2, r1
142    cmpnei  r2, 0
143    bf      .L_loop1_done
144
145.L_loop1:
146    stw     r0, (r1, 0)
147    addi    r1, 4
148    subi    r2, 4
149    cmpnei  r2, 0
150    bt      .L_loop1
151.L_loop1_done:
152
153#ifdef CONFIG_SEPARATE_IRQ_SP
154    lrw     r0, g_top_irqstack
155    mtcr    r0, cr<15, 1>
156
157    mfcr    r0, cr<31, 0>
158    bseti   r0, 14
159    mtcr    r0, cr<31, 0>
160#endif
161
162#ifndef __NO_SYSTEM_INIT
163    bsr     SystemInit
164#endif
165
166//#ifndef __NO_BOARD_INIT
167//  bsr     board_init
168//#endif
169
170//VIC init...
171    lrw    r0, VIC_TSPR
172    movi   r1, 0xb00
173    stw    r1, (r0)
174
175    bsr entry
176
177__exit:
178    bkpt
179    .size   Reset_Handler, . - Reset_Handler
180
181    .align  1
182    .weak   Default_Handler
183    .type   Default_Handler, %function
184Default_Handler:
185    br      Default_Handler
186    .size   Default_Handler, . - Default_Handler
187
188.section .bss
189
190    .align  2
191    .globl  g_intstackalloc
192    .global g_intstackbase
193    .global g_top_irqstack
194g_intstackalloc:
195g_intstackbase:
196    .space CONFIG_ARCH_INTERRUPTSTACK
197g_top_irqstack:
198
199/*    Macro to define default handlers. Default handler
200 *    will be weak symbol and just dead loops. They can be
201 *    overwritten by other handlers */
202    .macro  def_irq_handler handler_name
203    .weak   \handler_name
204    .set    \handler_name, Default_Handler
205    .endm
206
207    def_irq_handler CORET_IRQHandler
208    def_irq_handler TIMA0_IRQHandler
209    def_irq_handler TIMA1_IRQHandler
210    def_irq_handler TIMB0_IRQHandler
211    def_irq_handler TIMB1_IRQHandler
212    def_irq_handler USART0_IRQHandler
213    def_irq_handler USART1_IRQHandler
214    def_irq_handler USART2_IRQHandler
215    def_irq_handler USART3_IRQHandler
216    def_irq_handler GPIOA_IRQHandler
217    def_irq_handler GPIOB_IRQHandler
218    def_irq_handler I2C0_IRQHandler
219    def_irq_handler I2C1_IRQHandler
220    def_irq_handler SPI0_IRQHandler
221    def_irq_handler SPI1_IRQHandler
222    def_irq_handler RTC_IRQHandler
223    def_irq_handler WDT_IRQHandler
224    def_irq_handler PWM_IRQHandler
225    def_irq_handler DMAC_IRQHandler
226    def_irq_handler AES_IRQHandler
227    def_irq_handler SHA_IRQHandler
228
229    .end
230
231