1 /* 2 * Copyright (c) 2006-2024, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024/11/26 zdtyuiop4444 The first version 9 */ 10 11 #ifndef __CACHE_H__ 12 #define __CACHE_H__ 13 14 #include <rthw.h> 15 16 #define L1_CACHE_BYTES 64 17 #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) 18 19 /* 20 * dcache.ipa rs1 (invalidate) 21 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 22 * 0000001 01010 rs1 000 00000 0001011 23 * 24 * dcache.cpa rs1 (clean) 25 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 26 * 0000001 01001 rs1 000 00000 0001011 27 * 28 * dcache.cipa rs1 (clean then invalidate) 29 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 30 * 0000001 01011 rs1 000 00000 0001011 31 * 32 * icache.ipa rs1 (invalidate) 33 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 34 * 0000001 11000 rs1 000 00000 0001011 35 * 36 * sync.s 37 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 38 * 0000000 11001 00000 000 00000 0001011 39 */ 40 41 #define DCACHE_IPA_A0 ".long 0x02a5000b" 42 #define DCACHE_CPA_A0 ".long 0x0295000b" 43 #define DCACHE_CIPA_A0 ".long 0x02b5000b" 44 #define ICACHE_IPA_A0 ".long 0x0385000b" 45 46 #define SYNC_S ".long 0x0190000b" 47 48 #define CACHE_OP_RANGE(OP, start, size) \ 49 register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1); \ 50 for (; i < ALIGN(start + size, L1_CACHE_BYTES); i += L1_CACHE_BYTES) \ 51 __asm__ __volatile__(OP); \ 52 __asm__ __volatile__(SYNC_S) 53 54 #endif /* __CACHE_H__ */ 55